Spin dependent tunneling memory

Claim 2

A ferromagnetic thin-film based digital memory circuit, said circuit comprising: a pair of switching devices, each having first and second terminating regions and a control region by which that said switching device is capable of being directed to provide a conductive path between that said switching device first and second terminating regions of a selected conductivity; a pair of load devices each capable of conducting current therethrough to result in a voltage drop thereacross and each electrically connected in series with said second terminating region of a corresponding one of said plurality of switching devices and interconnection means suited for electrical connection to a source of electrical energization, said pair of load devices each also being coupled to a control region of that one of said pair of switching devices opposite that with which it is electrically connected in series; and a pair of bit structures each coupled to a corresponding one of said pair of load devices so as to result in different value voltages at said control regions of said pair of switching devices for selected increases in voltage magnitude on said interconnection means, said bit structures comprising: a nonmagnetic intermediate layer, said intermediate layer having two major surfaces on opposite sides thereof such; and a memory film of an anisotropic ferromagnetic material on each of said intermediate layer major surfaces having switching thresholds for magnetizations of said film adjacent each of said intermediate layer major surfaces that differ in value for a switching of these magnetizations from both being directed initially at least in part in substantially a common direction to being directed at least in part in substantially opposite directions versus a switching from being directed initially at least in part in substantially opposite directions to both being directed at least in part in substantially a common direction, and a pair of word line structures each having a pair of word line end terminal regions adapted to conduct electrical current in at least one direction therethrough, each of said pairs of word line end terminal regions having an electrical conductor electrically connected therebetween which is located across an electrical insulating layer from said memory film on one of said major surfaces of said intermediate layer of a corresponding one of said bit structures.

Claim 3

The apparatus of claim 1 wherein said pair of bit structures each is electrically connected between one of said pair of load devices and a said control region of one of said switching devices.

Claim 4

The apparatus of claim 1 wherein said pair of bit structures each is electrically connected between one of said pair of load devices and a said second terminating region of one of said switching devices.

Claim 5

The apparatus of claim 1 wherein a said bit structure has a length along a selected direction and a width substantially perpendicular thereto that is smaller in extent than said length, said memory film in a said bit structure being characterized by an anisotropy field, and said width being sufficiently small that demagnetization fields arising in said memory film in response to its saturation magnetization being oriented along that said width exceed in magnitude said anisotropy field.

Claim 6

The apparatus of claim 1 wherein a said bit structure has a length along a selected direction and a width substantially perpendicular thereto that is smaller in extent than said length and has a shaped end portion extending over a portion of said length in which said width gradually reduces to zero at an end thereof.

Claim 7

The apparatus of claim 1 wherein said memory film at each of said major surfaces of said intermediate layer of at least one of said bit structures is arranged such that there are two separate films with one of said separate films on each of said major surfaces, and said intermediate is also of an electrical insulating kind of material.

Claim 8

The apparatus of claim 6 wherein said bit structure has a length along selected direction and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

Claim 9

The apparatus of claim 6 wherein said memory film at each of said major surfaces is a composite film having a thinner stratum of higher magnetic saturation induction adjacent said intermediate material and a thicker stratum of lower magnetic saturation induction.

Claim 10

A ferromagnetic thin-film based digital memory circuit, said circuit comprising: a pair of switching devices, each having first and second terminating regions and a control region by which that said switching device is capable of being directed to provide a conductive path between that said switching device first and second terminating regions of a selected conductivity; a pair of load devices each capable of conducting current therethrough to result in a voltage drop thereacross and each electrically connected in series with said second terminating region of a corresponding one of said plurality of switching devices and interconnection means suited for electrical connection to a source of electrical energization, said pair of load means each also being coupled to a control region of that one of said pair of switching devices opposite that with which it is electrically connected in series; and a pair of bit structures each electrically connected in series with said second terminating region of a corresponding one of said plurality of switching devices so as to result in different value voltages at said control regions of said pair of switching devices for selected increases in voltage magnitude on said interconnection devices, said bit structures comprising: a nonmagnetic intermediate layer, said intermediate layer having two major surfaces on opposite sides thereof; and a memory film of an anisotropic ferromagnetic material on each of said intermediate layer major surfaces having switching thresholds for magnetizations of said film adjacent each of said intermediate layer major surfaces that differ in value for a switching of these magnetizations from both being directed initially at least in part in substantially a common direction to being directed at least in part in substantially opposite directions versus a switching from being directed initially at least in part in substantially opposite directions to both being directed at least in part in substantially a common direction, and a pair of word line structures each having a pair of word line end terminal regions adapted to conduct electrical current in at least one direction therethrough, each of said pairs of word line end terminal regions having an electrical conductor electrically connected therebetween which is located across an electrical insulating layer from said memory film on one of said major surfaces of said intermediate layer of a corresponding one of said bit structures.

Claim 11

A ferromagnetic thin-film based digital memory circuit, said circuit comprising: a pair of switching devices, each having first and second terminating regions and a control region by which that said switching device is capable of being directed to provide a conductive path between that said switching device first and second terminating regions of a selected conductivity; a pair of load devices each capable of conducting current therethrough to result in a voltage drop thereacross and each electrically connected in series with said second terminating region of a corresponding one of said plurality of switching devices and interconnection means suited for electrical connection to a source of electrical energization, said pair of load means each also being coupled to a control region of that one of said pair of switching devices opposite that with which it is electrically connected in series; and a pair of bit structures each electrically connected in series with said second terminating region of a corresponding one of said plurality of switching devices so as to result in different value voltages at said control regions of said pair of switching devices for selected increases in voltage magnitude on said interconnection devices, said bit structures comprising: a nonmagnetic intermediate layer, said intermediate layer having two major surfaces on opposite sides thereof; and a memory film of an anisotropic ferromagnetic material on each of said intermediate layer major surfaces having switching thresholds for magnetizations of said film adjacent each of said intermediate layer major surfaces that differ in value for a switching of these magnetizations from both being directed initially at least in part in substantially a common direction to being directed at least in part in substantially opposite directions versus a switching from being directed initially at least in part in substantially opposite directions to both being directed at least in part in substantially a common direction, and a pair of word line structures each having a pair of word line end terminal regions adapted to conduct electrical current in at least one direction therethrough, each of said pairs of word line end terminal regions having an electrical conductor electrically connected therebetween which is located across an electrical insulating layer from said memory film on one of said major surfaces of said intermediate layer of a corresponding one of said bit structures.

Claim 12

The apparatus of claim 9 wherein a said bit structure has a length along a selected direction and a width substantially perpendicular thereto that is smaller in extent than said length, said memory film in a said bit structure being characterized by an anisotropy field, and said width being sufficiently small that demagnetization fields arising in said memory film in response to its saturation magnetization being oriented along that said width exceed in magnitude said anisotropy field.

Claim 13

The apparatus of claim 9 wherein a said bit structure has a length along a selected direction and a width substantially perpendicular thereto that is smaller in extent than said length and has a shaped end portion extending over a portion of said length in which said width gradually reduces to zero at an end thereof.

Claim 14

The apparatus of claim 9 wherein said memory film at each of said major surfaces of said intermediate layer of at least one of said bit structures is arranged such that there are two separate films with one of said separate films on each of said major surfaces, and said intermediate layer is of an electrical insulating kind of material.

Claim 15

The apparatus of claim 12 wherein said bit structure has a length along selected direction and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

Claim 16

The apparatus of claim 12 wherein said memory film at each of said major surfaces is a composite film having a thinner stratum of higher magnetic saturation induction adjacent said intermediate material and a thicker stratum of lower magnetic saturation induction.