Nonvolatile memory device having ferroelectric film

Claim 2

A nonvolatile memory device comprising a flip flop circuit which includes (a) a first field effect transistor to which specified supply voltage is applied, (b) a second field effect transistor to which said specified supply voltage is applied, (c) a third field effect transistor having one end connected to the first field effect transistor and having the other end to which specified voltage is applied, and (d) a fourth field effect transistor having one end connected to the second field effect transistor and having the other end to which said specified voltage is applied; a first node between the first field effect transistor and the third field effect transistor being connected to gates of the second and fourth field effect transistors; a second node between the second field effect transistor and the fourth field effect transistor being connected to gates of the first and third field effect transistors; the first and third field effect transistors complementarily operating; the second and fourth field effect transistors complementarily operating; and the first, second, third and fourth field effect transistors having respective ferroelectric gate films; data writing means, applying writing voltages corresponding to complementary data to said first and second nodes, and developing a polarization in each of said ferroelectric gate films of said first, second, third and fourth field effect transistors in individual specified directions, for writing data in said flip flop circuit; data reading means detecting a potential difference between said first node and said second node for reading stored data; a first reading/writing transistor connected to said first node; a second reading/writing transistor connected to said second node; and means for turning said first and second reading/writing transistors on in writing or reading data; said data writing means applying writing voltage to the gates of said first, second, third and fourth field effect transistors through said first and second reading/writing transistors; and said data reading means detecting a potential difference between said first node and said second node through said first and second reading/writing transistors.

Claim 3

A nonvolatile memory device according to claim 1, wherein said first and second reading/writing transistors have high voltage sustainability, so that the writing voltage, at a level sufficient to invert the polarity of the ferroelectric films of the first, second, third and fourth field effect transistors, is transmitted by said first and second reading/writing transistors.

Claim 4

A nonvolatile memory device according to claim 1, wherein each of said first, second, third and fourth field effect transistors includes a source region and a drain region formed in a semiconductor substrate at an interval; a channel region between said source region and said drain region; a ferroelectric gate film formed on said channel region; and a gate electrode formed on said ferroelectric gate film.

Claim 5

A nonvolatile memory device according to claim 3, wherein said ferroelectric gate film is formed in contact with said semiconductor substrate.

Claim 6

A nonvolatile memory device according to claim 3, wherein a gate insulating film is sandwiched between said ferroelectric gate film and said semiconductor substrate.

Claim 7

A nonvolatile memory device according to claim 5, wherein a metal layer is sandwiched between said ferroelectric gate film and said gate insulating film.

Claim 8

A nonvolatile memory device comprising a plurality of memory cells arranged in a matrix manner on a semiconductor substrate, each comprised respectively of (A) a flip flop circuit which includes (a) a first field effect transistor to which specified supply voltage is applied, (b) a second field effect transistor to which said specified supply voltage is applied, (c) a third field effect transistor having one end connected to the first field effect transistor and having the other end to which specified voltage is applied, and (d) a fourth field effect transistor having one end connected to the second field effect transistor and having the other end to which said specified voltage is applied; a first node between the first field effect transistor and the third field effect transistor being connected to gates of the second and fourth field effect transistors; a second node between the second field effect transistor and the fourth field effect transistor being connected to gates of the first and third field effect transistors; the first and third field effect transistors complementarily operating; the second and fourth field effect transistors complementarily operating; and the first, second, third and fourth field effect transistors having respective ferroelectric gate films; (B) a first reading/writing transistor connected to said first node; and (C) a second reading/writing transistor connected to said second node; a word line means connected to gates of said first and second reading/writing transistors of each memory cell arranged in a row; a first bit line connected to said first reading/writing transistors on their ends opposite to said first node, in the memory cells arranged in a column; a second bit line connected to the second reading/writing transistors on their ends opposite to said second node, in the memory cells arranged in a column; means for selecting any one of the memory cells; means for applying voltage to said word line means to turn said first reading/writing transistor on in writing data in the selected memory cell or in reading data from the selected memory cell; means for applying voltage to said word line means to turn said second reading/writing transistor on in writing data in the selected memory cell or in reading data from the selected memory cell; data writing means for writing data in said flip flop circuit, said data writing means applying writing voltages corresponding to complementary data to the first and second bit lines, and developing a polarization in each of said ferroelectric gate films of said first, second, third and fourth field effect transistors in the selected memory cell in individual specified directions, for writing data in the selected memory cell; and data reading means for detecting a potential difference between the first bit line and the second bit line in reading data stored in the selected memory cell.

Claim 9

A nonvolatile memory device comprising a plurality of memory cells arranged in a matrix manner on a semiconductor substrate, each comprised respectively of (A) a flip flop circuit which includes (a) a first field effect transistor to which specified supply voltage is applied, (b) a second field effect transistor to which said specified supply voltage is applied, (c) a third field effect transistor having one end connected to the first field effect transistor and having the other end to which specified voltage is applied, and (d) a fourth field effect transistor having one end connected to the second field effect transistor and having the other end to which said specified voltage is applied; a first node between the first field effect transistor and the third field effect transistor being connected to gates of the second and fourth field effect transistors; a second node between the second field effect transistor and the fourth field effect transistor being connected to gates of the first and third field effect transistors; the first and third field effect transistors complementarily operating; the second and fourth field effect transistors complementarily operating; and the first, second, third and fourth field effect transistors having respective ferroelectric gate films; (B) a first reading/writing transistor connected to said first node; and (C) a second reading/writing transistor connected to said second node; a word line means connected to gates of said first and second reading/writing transistors of each memory cell arranged in a row; a first bit line connected to said first reading/writing transistors on their ends opposite to said first node, in the memory cells arranged in a column; a second bit line connected to the second reading/writing transistors on their ends opposite to said second node, in the memory cells arranged in a column; means for selecting any one of the memory cells; means for applying voltage to said word line means to turn said first reading/writing transistor on in writing data in the selected memory cell or in reading data from the selected memory cell; means for applying voltage to said word line means to turn said second reading/writing transistor on in writing data in the selected memory cell or in reading data from the selected memory cell; data writing means for writing data in said flip flop circuit, said data writing means applying writing voltages corresponding to complementary data to the first and second bit lines, and developing a polarization in each of said ferroelectric gate films of said first, second, third and fourth field effect transistors in the selected memory cell in individual specified directions, for writing data in the selected memory cell; and data reading means for detecting a potential difference between the first bit line and the second bit line in reading data stored in the selected memory cell.

Claim 10

A nonvolatile memory device according to claim 7, wherein said word line means comprise a common word line to which the gates of said first and second reading/writing transistors are connected.

Claim 11

A nonvolatile memory device according to claim 7, wherein said first and second reading/writing transistors have high voltage sustainability, so that the writing voltage, at a level sufficient to invert the polarity of the ferroelectric films of the first, second, third and fourth field effect transistors, is transmitted by said first and second reading/writing transistors.

Claim 12

A nonvolatile memory device according to claim 7, wherein each of said first, second, third and fourth field effect transistors includes a source region and a drain region formed in a semiconductor substrate at an interval; a channel region between said source region and said drain region; a ferroelectric gate film formed on said channel region; and a gate electrode formed on said ferroelectric gate film.

Claim 13

A nonvolatile memory device according to claim 10, wherein said ferroelectric gate film is formed in contact with said semiconductor substrate.

Claim 14

A nonvolatile memory device according to claim 10, wherein a gate insulating film is sandwiched between the ferroelectric gate film and the semiconductor substrate.

Claim 15

A nonvolatile memory device according to claim 12, wherein a metal layer is sandwiched between the ferroelectric gate film and the gate insulating film.