Patent US6469374B1 successfully refreshed from Google Patents.
US6469374B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Superposed printed substrates and insulating substrates having semiconductor elements inside
Assignee: Ibiden Co Ltd
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Filing: 2000-08-25
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Granted: 2002-10-22
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Expires: 2020-08-25
Abstract
Abstract A semiconductor device including superposed packages is disclosed, which comprises an superposed structure formed by superposing a plurality of superposed substrates each comprised of a wiring printed substrate loaded with a semiconductor element and a conductive-via provided insulating substrate, wherein the wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes and a plurality of wiring conductors electrically connected to the contact electrodes, the semiconductor element is electrically connected to wiring conductors provided on the wiring printed substrate, the insulating substrate includes a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on the wiring printed substrate and a plurality of contact electrodes, the conductive-via provided insulating substrate and the wiring printed substrate are superposed in such a manner that the contact electrode in the conductive-via provided insulating substrate and the contact electrode in the wiring printed substrate are electrically connected to each other and such that the semiconductor element loaded on the wiring printed substrate is accommodated in the chip cavity in the conductive-via provided insulating substrate so as to constitute a superposed substrate.
Inventors
- 👤 Takashi Imoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:37
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/401; H10W72/00; H10W72/01; H10W72/0198; H10W70/00; H10W70/60; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W90/20; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
240 words
A semiconductor device comprising a superposed structure formed by superposing a plurality of superposed substrates each including a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, wherein said wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in said wiring printed substrate in such a manner that said contact electrodes are buried in said via holes, and has a plurality of wiring conductors electrically connected to said contact electrodes, said semiconductor element loaded on said wiring printed substrate is electrically connected to said wiring conductors provided on said wiring printed substrate, said conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on said wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in said conductive-via provided insulating substrate in such a manner that said contact holes are buried in the via holes, and said conductive-via provided insulating substrate and said wiring printed substrate are superposed in such a manner that said contact electrodes in said conductive-via provided insulating substrate and said contact electrodes in said wiring printed substrate are electrically connected to each other and in such a manner that said semiconductor element loaded on said wiring printed substrate is accommodated in said chip cavity in said conductive-via provided insulating substrate to constitute a superposed substrate.
Claim 2
Dependent Claim
240 words
A semiconductor device comprising a superposed structure formed by superposing a plurality of superposed substrates each including a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, wherein said wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in said wiring printed substrate in such a manner that said contact electrodes are buried in said via holes, and has a plurality of wiring conductors electrically connected to said contact electrodes, said semiconductor element loaded on said wiring printed substrate is electrically connected to said wiring conductors provided on said wiring printed substrate, said conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on said wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in said conductive-via provided insulating substrate in such a manner that said contact holes are buried in the via holes, and said conductive-via provided insulating substrate and said wiring printed substrate are superposed in such a manner that said contact electrodes in said conductive-via provided insulating substrate and said contact electrodes in said wiring printed substrate are electrically connected to each other and in such a manner that said semiconductor element loaded on said wiring printed substrate is accommodated in said chip cavity in said conductive-via provided insulating substrate to constitute a superposed substrate.
Claim 3
Dependent Claim
20 words
A semiconductor device according to claim 1 , wherein said semiconductor element is substantially 30 to 200 μm in thickness.
Claim 4
Dependent Claim
41 words
A semiconductor device according to claim 1 , wherein a space for absorbing a stress is formed between said chip cavity of the inner conductive-via provided insulating substrate of said superposed substrate and said semiconductor element accommodated in the chip cavity.
Claim 5
Dependent Claim
17 words
A semiconductor device according to claim 3 , wherein said space is filled with flexible adhesive agent.
Claim 6
Dependent Claim
168 words
A semiconductor device according to claim 1 , further comprising a lower, outer conductive-via provided insulating substrate which is superposed on the wiring printed substrate of a lowermost superposed substrate, said outer conductive-via provided insulating substrate having a plurality of contact electrodes formed in a plurality of via holes formed in said outer conductive-via provided insulating substrate in such a manner that said contact electrodes are buried in the via holes, an upper surface of said lower conductive-via provided insulating substrate being in contact with the wiring printed substrate of said lowermost superposed substrate in such a manner that the plurality of contact electrodes of said lower conductive-via provided insulating substrate are electrically connected to the plurality of contact electrodes in the wiring printed substrate of said lowermost superposed substrate and a lower surface of said lower conductive-via provided insulating substrate having a plurality of external terminals connected to the plurality of contact electrodes formed in the plurality of the holes in said lower conductive-via provided insulating substrate.
Claim 7
Dependent Claim
41 words
A semiconductor device according to claim 5 , wherein a space for absorbing a stress is formed between said chip cavity of the inner conductive-via provided insulating substrate of said superposed substrate and said semiconductor element accommodated in the chip cavity.
Claim 8
Dependent Claim
17 words
A semiconductor device according to claim 6 , wherein said space is filled with flexible adhesive agent.
Claim 9
Dependent Claim
307 words
A semiconductor device comprising a superposed structure formed by superposing a plurality of superposed substrates each including a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, and including an upper, outer conductive-via provided insulating substrate which is superposed on the inner conductive-via provided insulating substrate of an uppermost superposed substrate and has a plurality of contact electrodes formed in a plurality of via holes formed in said upper conductive-via provided insulating substrate in such a manner that said contact electrodes are buried in the via holes, wherein said wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in said wiring printed substrate in such a manner that said contact electrodes are buried in said via holes and a plurality of wiring conductors electrically connected to said contact electrodes of said wiring printed substrate, said semiconductor element loaded on said wiring printed substrate is electrically connected to said wiring conductors provided on said wiring printed substrate, said inner conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on said wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in said inner conductive-via provided insulating substrate in such a manner said that contact electrodes are buried in the via holes, and said inner conductive-via provided insulating substrate and said wiring printed substrate are superposed in such a manner that said contact electrodes in said conductive-via provided insulating substrate and said contact electrodes in said wiring printed substrate are electrically connected to each other and in such a manner that said semiconductor element loaded on said wiring printed substrate is accommodated in said chip cavity in said conductive-via provided insulating substrate to constitute a superposed substrate.
Claim 10
Dependent Claim
307 words
A semiconductor device comprising a superposed structure formed by superposing a plurality of superposed substrates each including a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, and including an upper, outer conductive-via provided insulating substrate which is superposed on the inner conductive-via provided insulating substrate of an uppermost superposed substrate and has a plurality of contact electrodes formed in a plurality of via holes formed in said upper conductive-via provided insulating substrate in such a manner that said contact electrodes are buried in the via holes, wherein said wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in said wiring printed substrate in such a manner that said contact electrodes are buried in said via holes and a plurality of wiring conductors electrically connected to said contact electrodes of said wiring printed substrate, said semiconductor element loaded on said wiring printed substrate is electrically connected to said wiring conductors provided on said wiring printed substrate, said inner conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on said wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in said inner conductive-via provided insulating substrate in such a manner said that contact electrodes are buried in the via holes, and said inner conductive-via provided insulating substrate and said wiring printed substrate are superposed in such a manner that said contact electrodes in said conductive-via provided insulating substrate and said contact electrodes in said wiring printed substrate are electrically connected to each other and in such a manner that said semiconductor element loaded on said wiring printed substrate is accommodated in said chip cavity in said conductive-via provided insulating substrate to constitute a superposed substrate.
Claim 11
Dependent Claim
20 words
A semiconductor device according to claim 8 , wherein said semiconductor element is substantially 30 to 200 μm in thickness.
Claim 12
Dependent Claim
41 words
A semiconductor device according to claim 8 , wherein a space for absorbing a stress is formed between said chip cavity of the inner conductive-via provided insulating substrate of said superposed substrate and said semiconductor element accommodated in the chip cavity.
Claim 13
Dependent Claim
17 words
A semiconductor device according to claim 10 , wherein said space is filled with flexible adhesive agent.
Claim 14
Dependent Claim
168 words
A semiconductor device according to claim 8 , further comprising a lower, outer conductive-via provided insulating substrate which is superposed on the wiring printed substrate of a lowermost superposed substrate, said outer conductive-via provided insulating substrate having a plurality of contact electrodes formed in a plurality of via holes formed in said outer conductive-via provided insulating substrate in such a manner that said contact electrodes are buried in the via holes, an upper surface of said lower conductive-via provided insulating substrate being in contact with the wiring printed substrate of said lowermost superposed substrate in such a manner that the plurality of contact electrodes of said lower conductive-via provided insulating substrate are electrically connected to the plurality of contact electrodes in the wiring printed substrate of said lowermost superposed substrate and a lower surface of said lower conductive-via provided insulating substrate having a plurality of external terminals connected to the plurality of contact electrodes formed in the plurality of the holes in said lower conductive-via provided insulating substrate.
Claim 15
Dependent Claim
41 words
A semiconductor device according to claim 12 , wherein a space for absorbing a stress is formed between said chip cavity of the inner conductive-via provided insulating substrate of said superposed substrate and said semiconductor element accommodated in the chip cavity.
Claim 16
Dependent Claim
17 words
A semiconductor device according to claim 13 , wherein said space is filled with flexible adhesive agent.
References Cited (Backward Citations)
JPH05291318A
Cited
US6188127B1
Cited
JPH08236694A
Cited
JPH09219490A
Cited
US5744827A
Cited
JPH10163414A
Cited
JPH10135267A
Cited
JPH11145381A
Cited
US6180881B1
Cited
US6239495B1
Cited
US6274929B1
Cited
US6239496B1
Cited
US20010054758A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |