Delay locked loop circuit having duty cycle correction function and delay locking method

Claim 2

A delay locked loop circuit, comprising: a delaying portion for generating a first output signal by uniformly delaying an input first clock signal and generating a second output signal by variably delaying the first clock signal; an output signal generator for generating a second clock signal, a voltage level of which increases when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state; and an integrator for integrating the second clock signal and wherein the delaying portion generates the second output signal by variably delaying the first clock signal in response to an output signal of the integrator.

Claim 3

The delay locked loop circuit of claim 1 , wherein the first logic state of the first output signal is a logic “low” level and the second logic state of the first output signal is a logic “high” level.

Claim 4

The delay locked loop circuit of claim 1 , wherein the first logic state of the second output signal is the logic “low” level and the second logic state of the first output signal is the logic “high” level.

Claim 5

The delay locked loop circuit of claim 1 , wherein the delaying portion comprises: a first delay for delaying the first clock signal and generating the first output signal; and a second delay for generating the second output signal by variably delaying the first clock signal.

Claim 6

The delay locked loop circuit of claim 1 , wherein the output signal generator comprises: a first pulse signal generator for generating a first pulse signal when the first output signal transitions from the first logic state to the second logic state; a second pulse signal generator for generating a second pulse signal when the second output signal transitions from the second logic state to the first logic state; and a flip-flop for generating the second clock signal, the voltage level of which is increased when the first pulse signal is generated and the voltage level of which is reduced when the second pulse signal is generated.

Claim 7

A delay locked loop circuit, comprising: a delaying portion for generating first and second output signals by delaying an input first clock signal by a predetermined time period and by selectively varying the output time of the first and second output signals; an output signal generator for generating a second clock signal, a voltage level of which is increased when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state; and an integrator for integrating the second clock signal and wherein the delaying portion variably delays the output time in response to an output signal of the integrator.

Claim 8

A delay locked loop circuit, comprising: a delaying portion for generating first and second output signals by delaying an input first clock signal by a predetermined time period and by selectively varying the output time of the first and second output signals; an output signal generator for generating a second clock signal, a voltage level of which is increased when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state; and an integrator for integrating the second clock signal and wherein the delaying portion variably delays the output time in response to an output signal of the integrator.

Claim 9

The delay locked loop circuit of claim 6 , wherein the first logic state of the second output signal is a logic “low” level and the second logic state of the first output signal is a logic “high” level.

Claim 10

The delay locked loop circuit of claim 6 , wherein the first logic state of the second output signal is the logic “high” level and the second logic state of the first output signal is the logic “low” level.

Claim 11

The delay locked loop circuit of claim 6 , wherein the delaying portion comprises: a first multiplexer for receiving a reference voltage and a control signal and outputting either the reference voltage or the control signal in response to a selection signal; a first delay for generating a first output signal by controlling the delay time of an input first clock signal in response to the output of the first multiplexer; a second multiplexer for receiving the reference voltage and the control signal and outputting either the reference voltage or the control signal; and a second delay for generating a second output signal by controlling the delay time of the first clock signal in response to the output of the second multiplexer.

Claim 12

The delay locked loop circuit of claim 6 , wherein the output signal generator comprises: a first pulse signal generator for generating a first pulse signal when the first output signal is transitioned from a first logic state to a second logic state; a second pulse signal generator for generating a second pulse signal when the second output signal is transitioned from the second logic state to the first logic state; and a flip-flop for generating the second clock signal, the voltage level of which is increased when the first pulse signal is generated and the voltage level of which is reduced when the second pulse signal is generated.

Claim 13

The delay locked loop circuit of claim 9 , wherein the first delay uniformly delays the first clock signal when the first multiplexer outputs the reference voltage and variably delays the first clock signal when the second multiplexer outputs the control signal.

Claim 14

The delay locked loop circuit of claim 9 , wherein the reference voltage is half of a source voltage of the delay locked loop circuit.

Claim 15

A delay locking method, comprising the steps of: receiving a first clock signal; generating a first output signal by uniformly delaying the first clock signal; generating a second output signal by delaying the first clock signal for a first predetermined time; generating a second clock signal based on transitions of the first and second output signals, wherein: the second clock signal transitions from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state; and the second clock signal transitions from the logic “high” level to the logic “low” level when the second output signal is transitioned from the second logic state to the first logic state; and wherein generating the second output signal further comprises the step of integrating the second clock signal and wherein the first predetermined time delay of the generation of the second output signal varies in response to a signal generated by integrating the second clock signal.

Claim 16

A delay locking method, comprising the steps of: receiving a first clock signal; generating a first output signal by uniformly delaying the first clock signal; generating a second output signal by delaying the first clock signal for a first predetermined time; generating a second clock signal based on transitions of the first and second output signals, wherein: the second clock signal transitions from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state; and the second clock signal transitions from the logic “high” level to the logic “low” level when the second output signal is transitioned from the second logic state to the first logic state; and wherein generating the second output signal further comprises the step of integrating the second clock signal and wherein the first predetermined time delay of the generation of the second output signal varies in response to a signal generated by integrating the second clock signal.

Claim 17

A delay locking method, comprising the steps of: receiving a first clock signal; generating a first output signal by delaying the first clock signal for a first predetermined time; generating a second output signal by delaying the first clock signal for a second predetermined time; generating a second clock signal based on transitions of the first and second output signals, wherein: the second clock signal transitions from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state; and the second clock signal transitions from the logic “high” level to the logic “low” level when the second output signal is transitioned from the second logic state to the first logic state, wherein the output time of the second output signal is variable, when the output time of the first output signal is uniform and the output time of the second output signal is uniform when the output time of the first output signal is variable.

Claim 18

A delay locking method, comprising the steps of: receiving a first clock signal; generating a first output signal by delaying the first clock signal for a first predetermined time; generating a second output signal by delaying the first clock signal for a second predetermined time; generating a second clock signal based on transitions of the first and second output signals, wherein: the second clock signal transitions from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state; and the second clock signal transitions from the logic “high” level to the logic “low” level when the second output signal is transitioned from the second logic state to the first logic state, wherein the output time of the second output signal is variable, when the output time of the first output signal is uniform and the output time of the second output signal is uniform when the output time of the first output signal is variable.

Claim 19

The method of claim 14 , wherein each of the steps of generating the first and second output signals further comprises the step of integrating the second clock signal and the output times of the first and second output signals selectively vary in response to the signal generated by integrating the second clock signal.

Claim 20

A delay locked loop circuit, comprising: a delaying portion for generating first and second output signals by delaying an input first clock signal by a predetermined time period and by selectively varying the output time of the first and second output signals; an output signal generator for generating a second clock signal, a voltage level of which is increased when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state; wherein the delaying portion comprises: a first multiplexer for receiving a reference voltage and a control signal and outputting either the reference voltage or the control signal in response to a selection signal; a first delay for generating a first output signal by controlling the delay time of an input first clock signal in response to the output of the first multiplexer; a second multiplexer for receiving the reference voltage and the control signal and outputting either the reference voltage or the control signal; and a second delay for generating a second output signal by controlling the delay time of the first clock signal in response to the output of the second multiplexer.

Claim 21

A delay locked loop circuit, comprising: a delaying portion for generating first and second output signals by delaying an input first clock signal by a predetermined time period and by selectively varying the output time of the first and second output signals; an output signal generator for generating a second clock signal, a voltage level of which is increased when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state; wherein the delaying portion comprises: a first multiplexer for receiving a reference voltage and a control signal and outputting either the reference voltage or the control signal in response to a selection signal; a first delay for generating a first output signal by controlling the delay time of an input first clock signal in response to the output of the first multiplexer; a second multiplexer for receiving the reference voltage and the control signal and outputting either the reference voltage or the control signal; and a second delay for generating a second output signal by controlling the delay time of the first clock signal in response to the output of the second multiplexer.

Claim 22

The delay locked loop circuit of claim 16 , wherein the first delay uniformly delays the first clock signal when the first multiplexer outputs the reference voltage and variably delays the first clock signal when the second multiplexer outputs the control signal.

Claim 23

The delay locked loop circuit of claim 16 , wherein the reference voltage is half of a source voltage of the delay locked loop circuit.