US5815017A
Expired / Lapsed
US
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Forced oscillator circuit and method
Assignee: NXP USA Inc
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Filing: 1997-03-03
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Granted: 1998-09-29
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Expires: 2017-03-03
Abstract
Abstract An integrated circuit and method produce a first clock signal (CLOCK) from a reference clock (REFCLK) but at a different frequency. A variable delay line (32) produces the first clock signal by introducing a variable delay in the reference clock signal that is controlled by a programming signal generated in a counter (34). The programming signal is incremented by a second clock signal (UP) while transitions of a fixed delay clock signal lead transitions of the first clock signal. When the programming signal reaches the count of a rollover code (ROLLOVER), the programming signal is reset to a zero count to begin a new sequence. A calibration circuit (36, 38, 40, 42) determines the count of the programming signal needed to produce the rollover code when the variable delay is at least as great as one period of the reference clock signal.
Inventors
- 👤 Duncan A. McFarland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:41
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0807
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
100 words
An integrated circuit, comprising: a variable delay line coupled for receiving a first clock signal and providing a variable delay clock signal in response to a programming signal; a phase detector having a first input coupled for receiving the variable delay clock signal and a second input coupled for receiving a fixed delay clock signal; a programmable counter having a control input coupled to an output of the phase detector, and an output for providing the programming signal; and a fixed delay line coupled for delaying the first clock signal to produce the fixed delay clock signal at an output.
Claim 2
Dependent Claim
100 words
An integrated circuit, comprising: a variable delay line coupled for receiving a first clock signal and providing a variable delay clock signal in response to a programming signal; a phase detector having a first input coupled for receiving the variable delay clock signal and a second input coupled for receiving a fixed delay clock signal; a programmable counter having a control input coupled to an output of the phase detector, and an output for providing the programming signal; and a fixed delay line coupled for delaying the first clock signal to produce the fixed delay clock signal at an output.
Claim 3
Dependent Claim
21 words
The integrated circuit of claim 1, wherein the programmable counter has a clock input coupled for receiving a second clock signal.
Claim 4
Dependent Claim
44 words
The integrated circuit of claim 2, wherein a frequency of the second clock signal is less than a frequency of the first clock signal, and the second clock signal increments the programmable counter to increase a variable delay of the variable delay clock signal.
Claim 5
Dependent Claim
50 words
The integrated circuit of claim 3, wherein a control signal is produced at the output of the phase detector that resets the programmable counter to a zero count that adjusts the variable delay of the variable delay clock signal to equal a fixed delay of the fixed delay clock signal.
Claim 6
Dependent Claim
28 words
The integrated circuit of claim 4, wherein the control signal is produced when the variable delay is equivalent to at least one period of the first clock signal.
Claim 7
Dependent Claim
78 words
An integrated circuit, comprising: a first variable delay line coupled for receiving a first clock signal and providing a first variable delay clock signal in response to a first programming signal; a first programmable counter having an output for providing the first programming signal where the first programmable counter resets upon reaching a value of a rollover code; and a calibration circuit for setting the rollover code to represent at least one period of the first clock signal.
Claim 8
Dependent Claim
78 words
An integrated circuit, comprising: a first variable delay line coupled for receiving a first clock signal and providing a first variable delay clock signal in response to a first programming signal; a first programmable counter having an output for providing the first programming signal where the first programmable counter resets upon reaching a value of a rollover code; and a calibration circuit for setting the rollover code to represent at least one period of the first clock signal.
Claim 9
Dependent Claim
91 words
The integrated circuit of claim 6, wherein the calibration circuit includes: a second variable delay line coupled for receiving the first clock signal and providing a second variable delay clock signal in response to a second programming signal; a phase detector having a first input coupled for receiving the second variable delay clock signal and an second input coupled for receiving a fixed delay clock signal; and a counter having a clock input coupled to an output of the phase detector and a first output for providing the second programming signal.
Claim 10
Dependent Claim
18 words
The integrated circuit of claim 7, wherein the counter has a second output for providing the rollover code.
Claim 11
Dependent Claim
44 words
The integrated circuit of claim 8, wherein a control signal is produced at an output of the phase detector for incrementing the counter until a variable delay of the second variable delay line reaches said at least one period of the first clock signal.
Claim 12
Dependent Claim
35 words
The integrated circuit of claim 9, wherein the calibration circuit further comprises a fixed delay line having an input for receiving the first clock signal and an output for producing the fixed delay clock signal.
Claim 13
Dependent Claim
22 words
The integrated circuit of claim 10, wherein the first programmable counter has a clock input coupled for receiving a second clock signal.
Claim 14
Dependent Claim
48 words
The integrated circuit of claim 11, wherein a frequency of the second clock signal is greater than a frequency of the first clock signal, and the first programming signal is decremented by the second clock signal to reduce a variable delay of the first variable delay clock signal.
Claim 15
Independent Claim
82 words
A method of modifying a clock frequency, comprising the steps of: delaying a first clock signal in response to a programming signal to produce a variable delay clock signal; detecting a phase difference between the variable delay clock signal and a fixed delay clock signal to produce a control signal; and altering values of the programming signal until reset by the control signal to produce a frequency of the variable delay clock signal different from a frequency of the first clock signal.
Claim 16
Independent Claim
82 words
A method of modifying a clock frequency, comprising the steps of: delaying a first clock signal in response to a programming signal to produce a variable delay clock signal; detecting a phase difference between the variable delay clock signal and a fixed delay clock signal to produce a control signal; and altering values of the programming signal until reset by the control signal to produce a frequency of the variable delay clock signal different from a frequency of the first clock signal.
Claim 17
Dependent Claim
22 words
The method of claim 13, further comprising the step of delaying the first clock signal to produce the fixed delay clock signal.
Claim 18
Dependent Claim
24 words
The method of claim 14, wherein the step of altering includes a step of increasing a variable delay of the variable delay clock signal.
Claim 19
Dependent Claim
29 words
The method of claim 15, wherein the step of detecting includes producing the control signal when the variable delay is at least one period of the first clock signal.
Claim 20
Dependent Claim
41 words
The method of claim 16, wherein the step of altering includes a step of incrementing the values of the programming signal with a second clock signal to produce the variable delay clock signal at a frequency of the second clock signal.
References Cited (Backward Citations)
US4780681A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |