Patent US6456961B1 successfully refreshed from Google Patents.
US6456961B1
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Method and apparatus for creating testable circuit designs having embedded cores
Assignee: Mentor Graphics Corp
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Filing: 1999-04-30
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Granted: 2002-09-24
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Expires: 2019-04-30
Abstract
Abstract A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
Inventors
- 👤 Srinivas Patil
- 👤 Wu-Tung Cheng
- 👤 Paul J. Reuter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
81 words
A computer-implemented method for creating a testable circuit design that includes one or more embedded cores, the method comprising: automatically identifying an embedded core within the testable circuit design, the embedded core having pins connecting the core internally within the circuit design; automatically associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design.
Claim 2
Dependent Claim
81 words
A computer-implemented method for creating a testable circuit design that includes one or more embedded cores, the method comprising: automatically identifying an embedded core within the testable circuit design, the embedded core having pins connecting the core internally within the circuit design; automatically associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein identifying an embedded core comprises examining a core test description file associated with the embedded core.
Claim 4
Dependent Claim
27 words
The method of claim 1 where in associating certain pins with circuit design pins includes storing in a core test access file information that describes the association.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein inserting access circuitry includes inserting a hierarchical block of access circuitry.
Claim 6
Dependent Claim
25 words
The method of claim 1 wherein the access circuitry inserted into the circuit design includes a decoder for sequentially accessing embedded cores to be tested.
Claim 7
Dependent Claim
18 words
The method of claim 1 wherein the access circuitry inserted into the circuit design comprises parallel access circuitry.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein the access circuitry inserted into the circuit design comprises serial access circuitry.
Claim 9
Dependent Claim
54 words
The method claim 1 including: providing test vectors for the embedded core, the test vectors applicable to the pins of the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
Claim 10
Dependent Claim
14 words
A computer-readable medium having computer-executable instructions for performing the acts of claim 1 .
Claim 11
Dependent Claim
31 words
The method of claim 1 wherein the automatically identifying and the automatically associating comprise running an executable computer program with inputs that include a netlist and a core test description file.
Claim 12
Dependent Claim
29 words
The method of claim 1 wherein the access circuitry includes a decoder that allows a specific core to be tested and other cores to be isolated and not tested.
Claim 13
Dependent Claim
69 words
A computer-implemented method for generating test vectors for a circuit design that includes one or more embedded cores, the method comprising: automatically identifying an association between certain pins of an embedded core and pins of the circuit design; and automatically generating test vectors for the circuit design by mapping core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
Claim 14
Dependent Claim
69 words
A computer-implemented method for generating test vectors for a circuit design that includes one or more embedded cores, the method comprising: automatically identifying an association between certain pins of an embedded core and pins of the circuit design; and automatically generating test vectors for the circuit design by mapping core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
Claim 15
Dependent Claim
73 words
The method of claim 12 wherein mapping core test vectors includes: if the certain pin of the embedded core has direct access to a pin of the circuit design, translate the vector stimulus/response for the certain pin to the circuit design pin; and if the certain pin of the embedded core has serial access to a pin of the circuit design, translate the vector stimulus/response for the certain pin to a scan operation.
Claim 16
Dependent Claim
13 words
A computer-readable medium computer-executable instructions for performing the acts of claim 12 .
Claim 17
Dependent Claim
29 words
The method of claim 12 wherein identifying the association between certain pins of the embedded core and pins of the circuit design comprises examining a core test access file.
Claim 18
Dependent Claim
95 words
A computer-readable medium having a tool for creating a testable circuit design that includes one or more embedded cores, the tool comprising: an automatic core-identifying mechanism that identifies an embedded core within the circuit design, the embedded core having pins connecting the core internally within the circuit design; an automatic mapping mechanism that associates certain pins of the embedded core with pins of the circuit design; and a circuitry insertion mechanism that inserts into the circuit design access circuitry coupling the certain pins of the embedded core to the associated pins of the circuit design.
Claim 19
Dependent Claim
95 words
A computer-readable medium having a tool for creating a testable circuit design that includes one or more embedded cores, the tool comprising: an automatic core-identifying mechanism that identifies an embedded core within the circuit design, the embedded core having pins connecting the core internally within the circuit design; an automatic mapping mechanism that associates certain pins of the embedded core with pins of the circuit design; and a circuitry insertion mechanism that inserts into the circuit design access circuitry coupling the certain pins of the embedded core to the associated pins of the circuit design.
Claim 20
Dependent Claim
68 words
The computer-readable medium of claim 16 including: a core test vector file for the embedded core, the test vectors applicable to the pins of the embedded core; and a test vector generating mechanism that generates test vectors for the circuit design by mapping test vectors from the core test vector file applicable to the certain pins of the embedded core to the associated pins of the circuit design.
Claim 21
Dependent Claim
82 words
A computer-readable medium having a tool for generating test vectors for a circuit design that includes one or more embedded cores, the tool comprising: an automatic identifying mechanism that identifies an association between certain pins of an embedded core and pins of the circuit design; and an automatic test vector generating mechanism that generates test vectors for the circuit design by mapping core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
Claim 22
Dependent Claim
82 words
A computer-readable medium having a tool for generating test vectors for a circuit design that includes one or more embedded cores, the tool comprising: an automatic identifying mechanism that identifies an association between certain pins of an embedded core and pins of the circuit design; and an automatic test vector generating mechanism that generates test vectors for the circuit design by mapping core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-23 | 2006-03-25 | 2006-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-23 | 2010-03-25 | 2010-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-23 | 2014-03-25 | 2014-09-24 | $7700.00 | Window Closed / Lapsed |