US5991898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arithmetic built-in self test of multiple scan-based integrated circuits
Assignee: Mentor Graphics Corp
•
Filing: 1997-03-10
•
Granted: 1999-11-23
•
Expires: 2017-03-10
Abstract
Abstract An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.
Inventors
- 👤 Janusz Rajski
- 👤 Jerzy Tyszer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2221; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
51 words
An apparatus comprising: a processor core including data paths; a plurality of peripheral devices having associated parallel scan registers coupled to the processor core; and operating logic for generating pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme, and using the data paths of the processor core.
Claim 2
Independent Claim
51 words
An apparatus comprising: a processor core including data paths; a plurality of peripheral devices having associated parallel scan registers coupled to the processor core; and operating logic for generating pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme, and using the data paths of the processor core.
Claim 3
Dependent Claim
112 words
The apparatus as set forth in claim 1, wherein the operating logic includes operating logic for multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.
Claim 4
Dependent Claim
46 words
The apparatus as set forth in claim 2, wherein the operating logic further includes operating logic for copying the n least significant bits of the new 2n-bit pseudo-random number into the first register, and right shifting the 2n-bit new pseudo-random number in the accumulator by n-bits.
Claim 5
Dependent Claim
44 words
The apparatus as set forth in claim 3, wherein the operating logic further includes operating logic for repeating said multiplying, adding, outputting, copying and right shifting sufficient number of times to generate a sufficiently large pseudo-random test pattern to fill the parallel scan registers.
Claim 6
Dependent Claim
35 words
The apparatus as set forth in claim 2, wherein the operating logic further includes operating logic for storing a 2n-bit initial value into the accumulator, and storing the n-bit multiplier constant in the second register.
Claim 7
Dependent Claim
110 words
The apparatus as set forth in claim 5, wherein the variable n, the 2n-bit initial value and the n-bit multiplier constant are equal to (3, 6, 1), (3, 6, 5), (4, 15, 1), (4, 15, 7), (5, 27, 1), (5, 27, 5), (6, 45, 1), (6, 45, 7), (7, 126, 1), (7, 126, 5), (8, 249, 1), (8, 249, 5), (9, 507, 1) (9, 507, 5), (10, 1020, 1), (10, 1020, 5), (11, 2016, 1), (11, 2016, 5), (12, 4077, 1), (12, 4077, 7), (13, 8175, 1), (13, 8175, 7), (14, 16371, 1), (14, 16371, 5), (15, 32766, 1), (15, 32766, 5), (16, 65514, 1), or (16, 65514, 5) respectively.
Claim 8
Dependent Claim
66 words
The apparatus as set forth in claim 2, wherein the apparatus further comprises a test port register through which the parallel scan registers are coupled to the processor core, and the operating logic further includes operating logic for moving a pseudo-random test vector from the processor core to the test port register, and then moving the pseudo-random test vector in parallel to the parallel scan registers.
Claim 9
Dependent Claim
45 words
The apparatus as set forth in claim 7, wherein the test port register comprises a plurality of output ports correspondingly coupled to first cells of the parallel scan registers, and a plurality of input ports correspondingly coupled to last cells of the parallel scan registers.
Claim 10
Dependent Claim
41 words
The apparatus as set forth in claim 7, wherein the operating logic further includes operating logic for applying one or more clock cycles to the peripheral devices to apply the test pattern in the parallel scan registers to the peripheral devices.
Claim 11
Dependent Claim
33 words
The apparatus as set forth in claim 7, wherein the operating logic further includes operating logic for moving test responses of the peripheral devices from the test port register to the processor core.
Claim 12
Dependent Claim
46 words
The apparatus of claim 1 wherein the operating logic is further for generating deterministic test patterns for the peripheral devices, emulating a plurality of linear feedback shift register (LFSR)-based segments interconnected by a network of linear functions, and using the data paths of the processor core.
Claim 13
Dependent Claim
68 words
The apparatus as set forth in claim 11, wherein the operating logic includes operating logic for modifying n×L storage locations of a circular buffer formed with L registers, each having n storage locations, emulating shifting of the content of the LFSR-based segments, and outputting the content of a head one of the L registers as a portion of a deterministic test pattern being generated for the peripheral devices.
Claim 14
Dependent Claim
40 words
The apparatus as set forth in claim 12, wherein the operating logic further includes operating logic for repeating said modification and outputting sufficient number of times to generate a sufficiently large deterministic test pattern to fill the parallel scan registers.
Claim 15
Dependent Claim
30 words
The apparatus as set forth in claim 12, wherein the operating logic further includes operating logic for advancing a head pointer for identifying the head one of the L registers.
Claim 16
Dependent Claim
39 words
The apparatus as set forth in claim 11, wherein the operating logic generates the deterministic test patterns emulating LFSR-based segments interconnected with a network of linear functions that implements an identical feedback polynomial for each of the LFSR-based segments.
Claim 17
Dependent Claim
39 words
The apparatus as set forth in claim 11, wherein the operating logic generates the deterministic test patterns emulating LFSR-based segments interconnected with a network of linear functions that provides inter-segment feedback at identical tap positions of the LFSR-based segments.
Claim 18
Dependent Claim
66 words
The apparatus as set forth in claim 11, wherein the apparatus further comprises a test port register through which the parallel scan registers are coupled to the processor core, and the operating logic further includes operating logic for moving a deterministic test vector from the processor core to the test port register, and then moving the pseudo-random test vector in parallel to the parallel scan registers.
Claim 19
Dependent Claim
32 words
The apparatus of claim 1 wherein the operating logic is further for compacting test responses from the peripheral devices, employing a cascaded approach, and using the data paths of the processor core.
Claim 20
Dependent Claim
61 words
The apparatus as set forth in claim 18, wherein the operating logic includes operating logic for moving a first test response into a first accumulator, adding a first signature to the first accumulator, moving a second test response into a second accumulator, outputting the content of the first accumulator and adding the output of the first accumulator into the second accumulator.
Claim 21
Dependent Claim
68 words
The apparatus as set forth in claim 19, wherein the operating logic further includes operating logic for moving the second test response into the first accumulator, adding a second signature that includes the first test response into the first accumulator, moving a third test response into the second accumulator, outputting the content of the first accumulator, and adding the output of the first accumulator to the second accumulator.
Claim 22
Dependent Claim
30 words
The apparatus as set forth in claim 20, wherein the operating logic adds the output of the first accumulator into the second accumulator in accordance with a 1's complement convention.
Claim 23
Dependent Claim
28 words
The apparatus as set forth in claim 20, wherein the operating logic adds the output of the first accumulator into the second accumulator using a rotate carry scheme.
Claim 24
Dependent Claim
55 words
The apparatus as set forth in claim 18, wherein the apparatus further comprises a test port register through which the parallel scan registers are coupled to the processor core, and the operating logic further includes operating logic for moving a test response of the peripheral devices from the test port register to the processor core.
Claim 25
Dependent Claim
39 words
The apparatus as set forth in claim 23, wherein the test response of the peripheral devices is recovered in the test port register as an integral part of storing a test vector in parallel into the parallel scan registers.
Claim 26
Dependent Claim
57 words
The apparatus of claim 1 wherein the operating logic is further for placing the processor core in a test mode, saving a pre-test state of the parallel scan registers, applying a plurality of test patterns to the peripheral devices using the data paths of the processor core, and restoring the pre-test state of the parallel scan registers.
Claim 27
Independent Claim
109 words
A method for generating pseudo-random test patterns comprising the steps of: multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for a plurality of peripheral devices.
Claim 28
Independent Claim
109 words
A method for generating pseudo-random test patterns comprising the steps of: multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for a plurality of peripheral devices.
Claim 29
Dependent Claim
45 words
The method as set forth in claim 26, wherein the method further includes the step of copying the n least significant bits of the new 2n-bit pseudo-random number into the first register, and right shifting the 2n-bit new pseudo-random number in the accumulator by n-bits.
Claim 30
Dependent Claim
46 words
The method as set forth in claim 27, wherein the method further includes the step of repeating said multiplying, adding, outputting, copying and right shifting steps sufficient number of times to generate a sufficiently large pseudo-random test pattern to fill a plurality of parallel scan registers.
Claim 31
Dependent Claim
34 words
The method as set forth in claim 26, wherein the method further includes the step of storing a 2n-bit initial value into the accumulator, and storing the n-bit multiplier constant in the second register.
Claim 32
Dependent Claim
110 words
The method as set forth in claim 29, wherein the variable n, the 2n-bit initial value and the n-bit multiplier constant are equal to (3, 6, 1), (3, 6, 5), (4, 15, 1), (4, 15, 7), (5, 27, 1), (5, 27, 5), (6, 45, 1), (6, 45, 7), (7, 126, 1), (7, 126, 5), (8, 249, 1), (8, 249, 5), (9, 507, 1) (9, 507, 5), (10, 1020, 1), (10, 1020, 5), (11, 2016, 1), (11, 2016, 5), (12, 4077, 1), (12, 4077, 7), (13, 8175, 1), (13, 8175, 7), (14, 16371, 1), (14, 16371, 5), (15, 32766, 1), (15, 32766, 5), (16, 65514, 1), or (16, 65514, 5) respectively.
Claim 33
Dependent Claim
42 words
The method as set forth in claim 26, wherein the method further comprises the step of moving a pseudo-random test vector to a test port register, and then moving the pseudo-random test vector in parallel to a plurality of parallel scan registers.
Claim 34
Dependent Claim
65 words
The method of claim 26 further comprising generating deterministic test patterns comprising the steps of: modifying n×L storage locations of a circular buffer formed with L registers, each having n storage locations, emulating shifting of the content of a plurality of LFSR-based segments, and outputting the content of a head one of the L registers as a portion of a deterministic test pattern being generated.
Claim 35
Dependent Claim
45 words
The method as set forth in claim 32, wherein the method further includes the step of repeating said modifying and said outputting the content a sufficient number of times to generate a sufficiently large deterministic test pattern to fill a plurality of parallel scan registers.
Claim 36
Dependent Claim
29 words
The method as set forth in claim 32, wherein the method further includes the step of advancing a head pointer for identifying the head one of the L registers.
Claim 37
Dependent Claim
36 words
The method as set forth in claim 32, wherein the emulation step emulates shifting of LFSR-based segments interconnected with a network of linear functions that implements an identical feedback polynomial for each of the LFSR-based segments.
Claim 38
Dependent Claim
36 words
The method as set forth in claim 32, wherein the emulation step emulates shifting of LFSR-based segments interconnected with a network of linear functions that provides inter-segment feedback at identical tap positions of the LFSR-based segments.
Claim 39
Dependent Claim
42 words
The method as set forth in claim 32, wherein the method further comprises the steps of moving a deterministic test vector to a test port register, and then moving the deterministic test vector in parallel to the plurality of parallel scan registers.
Claim 40
Dependent Claim
55 words
The method of claim 26 further comprising the steps of: moving a first test response into a first accumulator, adding a first signature to the first accumulator, moving a second test response into a second accumulator, outputting the content of the first accumulator and adding the output of the first accumulator into the second accumulator.
Claim 41
Dependent Claim
67 words
The method as set forth in claim 38, wherein the method further includes the step of: moving the second test response into the first accumulator, adding a second signature that includes the first test response into the first accumulator, moving a third test response into the second accumulator, outputting the content of the first accumulator, and adding the output of the first accumulator to the second accumulator.
Claim 42
Dependent Claim
33 words
The method as set forth in claim 39, wherein the step of adding of the output of the first accumulator into the second accumulator is performed in accordance with a 1's complement convention.
Claim 43
Dependent Claim
30 words
The method as set forth in claim 39, wherein the step of adding the output of the first accumulator into the second accumulator is performed using a rotate carry scheme.
Claim 44
Dependent Claim
26 words
The method as set forth in claim 38, wherein the method further comprises the step of moving a partial test response from a test port register.
Claim 45
Dependent Claim
36 words
The method as set forth in claim 42, wherein the step of moving the partial test response is performed as an integral part of a step of providing a test vector from the test port register.
Claim 46
Dependent Claim
118 words
The method of claim 26 further wherein the test patterns are generated using mission data paths of a processor core, and the test patterns are used for testing peripheral devices of an integrated circuit, the method further comprising the steps of: loading a plurality of parallel scan registers with a first set of test patterns from a test port register, one bit slice for each scan register at a time, and simultaneously recovering test responses for a previously generated second set of test patterns from the parallel scan registers into the test port register, one bit slice per scan register a time; moving the test responses into the processor core; and compacting the test responses into a signature.
Claim 47
Dependent Claim
43 words
The method as set forth in claim 44, wherein the method further includes the step of applying one or more clock cycles to the peripheral devices to apply the first set of test patterns in the parallel scan registers to the peripheral devices.
Claim 48
Dependent Claim
65 words
The method of claim 26 further comprising the steps of: placing a processor core in a test mode; saving a pre-test state of a plurality of parallel scan registers; applying a plurality of the test patterns to a plurality of peripheral devices using the data paths of the processor core and the parallel scan registers; and restoring the pre-test state of the parallel scan registers.
Claim 49
Dependent Claim
25 words
The method as set forth in claim 46 further comprising compacting test responses of the peripheral devices using the data paths of the processor core.
References Cited (Backward Citations)
US4511967A
Cited
US5226147A
Cited
US4947395A
Cited
US5369646A
Cited
US5239262A
Cited
US5590354A
Cited
US5416783A
Cited
US5724603A
Cited
US5617531A
Cited
US5790561A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |