Semiconductor integrated circuit device having test circuit

Claim 2

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein said plurality of selectively actuable switch means respectively comprise transistors, each provided between a corresponding one of the logic cells and a corresponding one of the interconnection lines, said transistors respectively having ON/OFF control terminals; and said semiconductor integrated circuit device comprises select means for selecting said logic cells for every column and for applying a select signal to the ON/OFF control terminals of said transistors related to a selected one of the columns so that said transistors related to said selected one of said columns are turned OFF when said logic cells related to said selected one of the columns are to be disconnected from corresponding interconnection lines of said interconnection lines and said desired data is to be respectively supplied to the input terminals of said logic cells connected to said transistors related to said selected one of the columns via said corresponding interconnection lines.

Claim 3

A semiconductor integrated circuit device as claimed in claim 1, further comprising control lines respectively provided for said columns, wherein said control lines couple the ON/OFF control terminals of said transistors and said select means, and respectively carry said column select signal.

Claim 4

A semiconductor integrated circuit device as claimed in claim 1, further comprising shift register means for outputting said desired data received from an external device to said plurality of selectively actuable switch means and for outputting data read out from said logic cells via said plurality of selectively actuable switch means to said external device.

Claim 5

A semiconductor integrated circuit device as claimed in claim 1, wherein each of said transistors is a field effect transistor having a gate terminal, and said ON/OFF control terminal corresponds to said gate terminal.

Claim 6

A semiconductor integrated circuit device as claimed in claim 1, further comprises a plurality of input/output buffers connected to the input terminals and output terminals of corresponding logic cells of said plurality of logic cells.

Claim 7

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein said plurality of selectively actuable switch means comprises transistors respectively provided for said logic cells, said transistors respectively having ON/OFF control terminals, and said desired data passing through said transistors and being applied to said interconnection lines via said transistors; and said semiconductor integrated circuit device comprises select means for selecting said logic cells for every row and for applying a row select signal to the ON/OFF control terminals of said transistors related to a selected one of the rows so that said desired data is respectively applied to corresponding interconnection lines of said interconnection lines via said transistors related to said selected one of the rows and then applied to the input terminals of said logic cells connected to said corresponding interconnection lines related to said selected one of the rows.

Claim 8

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein said plurality of selectively actuable switch means comprises transistors respectively provided for said logic cells, said transistors respectively having ON/OFF control terminals, and said desired data passing through said transistors and being applied to said interconnection lines via said transistors; and said semiconductor integrated circuit device comprises select means for selecting said logic cells for every row and for applying a row select signal to the ON/OFF control terminals of said transistors related to a selected one of the rows so that said desired data is respectively applied to corresponding interconnection lines of said interconnection lines via said transistors related to said selected one of the rows and then applied to the input terminals of said logic cells connected to said corresponding interconnection lines related to said selected one of the rows.

Claim 9

A semiconductor integrated circuit device as claimed in claim 6, further comprising control lines respectively provided for said rows, wherein said control lines couple the ON/OFF control terminals of said transistors and said select means, and respectively carry said row select signal.

Claim 10

A semiconductor integrated circuit device as claimed in claim 7, further comprising column read/write lines respectively provided for said columns, wherein said column read/write lines are coupled to the output terminals of said interconnection lines via said transistors.

Claim 11

A semiconductor integrated circuit device as claimed in claim 6, wherein each of said transistors is a field effect transistor having a gate terminal, and said ON/OFF control terminal corresponds to said gate terminal.

Claim 12

A semiconductor integrated circuit device as claimed in claim 6, further comprising shift register means for outputting said desired data received from an external device and for outputting data read out from said logic cells via said plurality of selectively actuable switch means to said external device.

Claim 13

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein said plurality of selectively actuable switch means respectively comprise analog switches, each provided between a corresponding one of the logic cells and a corresponding one of the interconnection lines, said analog switches respectively having ON/OFF control terminals; and said semiconductor integrated circuit device comprise select means for selecting said logic cells for every column and for applying a select signal to the ON/OFF control terminals of said analog switches related to a selected one of the columns so that said analog switches related to said selected one of the columns are turned OFF when said logic cells related to said selected one of the columns are to be disconnected for corresponding interconnection lines of said interconnection lines and said desired data is to be respectively supplied to the input terminals of said logic cells connected to said analog switches related to said selected one of the columns via said corresponding interconnection lines.

Claim 14

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein said plurality of selectively actuable switch means respectively comprise analog switches, each provided between a corresponding one of the logic cells and a corresponding one of the interconnection lines, said analog switches respectively having ON/OFF control terminals; and said semiconductor integrated circuit device comprise select means for selecting said logic cells for every column and for applying a select signal to the ON/OFF control terminals of said analog switches related to a selected one of the columns so that said analog switches related to said selected one of the columns are turned OFF when said logic cells related to said selected one of the columns are to be disconnected for corresponding interconnection lines of said interconnection lines and said desired data is to be respectively supplied to the input terminals of said logic cells connected to said analog switches related to said selected one of the columns via said corresponding interconnection lines.

Claim 15

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein each of said plurality of selectively actuable switch means comprises means for disconnecting a corresponding one of said logic cells from a pair of power sources.

Claim 16

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein each of said plurality of selectively actuable switch means comprises means for disconnecting a corresponding one of said logic cells from a pair of power sources.

Claim 17

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein each of said plurality of selectively actuable switch means comprises data setting means for setting the input terminal of a corresponding one of said logic cells to a desired logic level corresponding to said desired data via a corresponding one of said interconnection lines in a state where said corresponding one of the interconnection lines is disconnected from the input terminal of a corresponding one of said logic cells by a corresponding one of said plurality of switch means.

Claim 18

A semiconductor integrated circuit device, comprising: a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns, said logic cells respectively having input terminals and output terminals; interconnection lines mutually connecting said logic cells via said input and output terminals of the logic cells so that desired logic circuits are formed; a plurality of selectively actuable switch means, respectively provided for said logic cells, for selectively connecting the output terminals of each of said logic cells to said interconnection lines; and means for selectively directly supplying the input terminals of a selected one of said logic cells with desired data used for testing said semiconductor integrated circuit device; means for coordinating said data supply with control of said plurality of selectively actuable switch means to selectively disconnect the output terminals of said logic cells from said interconnection lines, and means for accessing said selected logic cell for evaluation of data within said cell; wherein each of said plurality of selectively actuable switch means comprises data setting means for setting the input terminal of a corresponding one of said logic cells to a desired logic level corresponding to said desired data via a corresponding one of said interconnection lines in a state where said corresponding one of the interconnection lines is disconnected from the input terminal of a corresponding one of said logic cells by a corresponding one of said plurality of switch means.

Claim 19

A semiconductor integrated circuit device as claimed in claim 13, further comprising: first control lines respectively provided for said columns; second control lines respectively provided for said rows; and select means for specifying said data setting means by selecting a corresponding one of said first control lines and a corresponding one of said second control lines and for making said data setting means set the input terminal of said corresponding one of the logic cells to said desired logic level.

Claim 20

A semiconductor integrated circuit device as claimed in claim 14, wherein said data setting means comprises: an AND gate having a first input terminal coupled to said corresponding one of the first control lines, a second input terminal coupled to said corresponding one of the second control lines, and an output terminal; a field effect transistor which is coupled between the output terminal of said AND gate and said corresponding one of the interconnection lines and which has a gate connected to the output terminal of said AND gate; and an inverter having an anode terminal connected to the gate of said field effect transistor, and a cathode terminal connected to a corresponding one of said plurality of selectively actuable switch means.

Claim 21

A semiconductor integrated circuit device as claimed in claim 15, wherein each of said plurality of selectively actuable switch means comprises a field effect transistor interposed between a corresponding one of said logic cells and said corresponding one of the interconnection lines, and a gate connected to the cathode terminal of said inverter.

Claim 22

A semiconductor integrated circuit device as claimed in claim 16, further comprising: column read lines respectively provided for said columns; a plurality of field effect transistors, each provided between a corresponding one of said logic cells and a corresponding one of said column read lines, data being read out from said corresponding one of the logic cells and output to said corresponding one of the column read lines, each of said field effect transistors having a gate; row select lines respectively provided for said rows, each of said row select lines being connected to the gate of a corresponding one of said field effect transistors; and row select means for selecting logic cells related to one of said rows from said logic cells.

Claim 23

A semiconductor integrated circuit device as claimed in claim 13, further comprising: first control lines respectively provided for said columns; second control lines respectively provided for said rows; third control lines respectively provided for said columns; and select means for specifying said data setting means by selecting a corresponding one of said first control lines, a corresponding one of said second control lines and a corresponding one of said third control lines and for making said data setting means set the input terminal of said corresponding one of the logic cells to said desired logic level.

Claim 24

A semiconductor integrated circuit device as claimed in claim 18, wherein said data setting means comprises: an AND gate having a first input terminal coupled to said corresponding one of the first control lines, a second input terminal coupled to said corresponding one of the second control lines, and an output terminal; a field effect transistor which is coupled between the output terminal of said AND gate and said corresponding one of the interconnection lines and which has a gate; and an inverter having a cathode terminal connected to the gate of said field effect transistor, and an anode terminal connected to a corresponding one of said plurality of selectively actuable switch means and a corresponding one of said third control lines.

Claim 25

A semiconductor integrated circuit device as claimed in claim 19, wherein each of said plurality of switch means comprises a field effect transistor interposed between a corresponding one of said logic cells and said corresponding one of the interconnection lines, and a gate connected to the anode terminal of said inverter and said corresponding one of the third control lines.

Claim 26

A semiconductor integrated circuit device as claimed in claim 20, further comprising: column read lines respectively provided for said columns; a plurality of field effect transistors, each provided between a corresponding one of said logic cells and a corresponding one of said column read lines, data being read out from said corresponding one of the logic cells and output to said corresponding one of the column read lines, each of said field effect transistors having a gate; row select lines respectively provided for said rows, each of said row select lines being connected to the gate of a corresponding one of said field effect transistors; and row select means for selecting logic cells related to one of said rows from said logic cells.