Patent US6444919B1 successfully refreshed from Google Patents.
US6444919B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin film wiring scheme utilizing inter-chip site surface wiring
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 2002-09-03
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Expires: 2015-06-07
Abstract
Abstract A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.
Inventors
- 👤 Laertis Economikos
- 👤 Mukta Shaji Farooq
- 👤 Michael Ford McAllister
- 👤 Eric Daniel Perfecto
- 👤 Chandrika Prasad
- 👤 Keshav Prasad
- 👤 Madhavan Swaminathan
- 👤 Thomas Anthony Wassick
- 👤 George White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:51
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; H05; H05K; H05K1/00; H05K1/02; H05K1/0286; H05K1/0287; H05K1/0289; H05K3/00; H05K3/46; H05K3/4644; H05K3/467
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
296 words
A thin film layer wiring scheme on a substrate comprising: at least two chip connection pads with an inter pad space at a first chip site on a thin film layer: a first chip site first directional wiring line interspersed between the first chip site chip connection pads; at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site; at least a first chip site second directional wiring line interspersed between the chip connection pads at the first chip site, wherein the first chip site first directional wiring lines and first chip site second directional wiring line are overlapping but not electrically contacting at the first chip site; at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces; a second chip site first directional wiring line interspersed between the second chip site chip connection pads; and at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.
Claim 2
Dependent Claim
296 words
A thin film layer wiring scheme on a substrate comprising: at least two chip connection pads with an inter pad space at a first chip site on a thin film layer: a first chip site first directional wiring line interspersed between the first chip site chip connection pads; at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site; at least a first chip site second directional wiring line interspersed between the chip connection pads at the first chip site, wherein the first chip site first directional wiring lines and first chip site second directional wiring line are overlapping but not electrically contacting at the first chip site; at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces; a second chip site first directional wiring line interspersed between the second chip site chip connection pads; and at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.
Claim 3
Dependent Claim
48 words
The wiring scheme of claim 1 wherein one of the first chip site first directional wiring lines at the first chip site is an X wiring line and one of the first chip site second directional wiring lines at the first chip site is a Y wiring line.
Claim 4
Dependent Claim
30 words
The wiring scheme of claim 1 wherein at least a portion of one of the first chip site second directional wiring line at the first chip site has been removed.
Claim 5
Dependent Claim
81 words
The wiring scheme of claim 1 wherein the overlapping first chip site second directional wiring line at the first chip site jogs underneath the first chip site first directional wiring lines, such jog comprising a traverse down to a subsurface portion of the thin film layer through a via, a traverse across the subsurface portion and underneath the other of the overlapping directional wiring lines and a traverse up to the one of the overlapping directional wiring lines through another via.
Claim 6
Dependent Claim
296 words
A thin film layer wiring scheme on a substrate comprising: at least two chip connection pads with an inter pad space at a first chip site on a thin film layer: a first chip site first directional wiring line interspersed between the first chip site chip connection pads; at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site; at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces; a second chip site first directional wiring line interspersed between the second chip site chip connection pads; wherein there is at least a second chip site second directional wiring line interspersed between the chip connection pads at the second chip site, the second chip site first directional wiring line and second chip site second directional wiring line overlapping but not contacting at the second chip site; and at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.
Claim 7
Dependent Claim
296 words
A thin film layer wiring scheme on a substrate comprising: at least two chip connection pads with an inter pad space at a first chip site on a thin film layer: a first chip site first directional wiring line interspersed between the first chip site chip connection pads; at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site; at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces; a second chip site first directional wiring line interspersed between the second chip site chip connection pads; wherein there is at least a second chip site second directional wiring line interspersed between the chip connection pads at the second chip site, the second chip site first directional wiring line and second chip site second directional wiring line overlapping but not contacting at the second chip site; and at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.
Claim 8
Dependent Claim
62 words
The wiring scheme of claim 1 or 5 wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on the top surface of the thin film layer.
Claim 9
Dependent Claim
60 words
The wiring scheme of claim 4 or 5 wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line are covered with a protective layer of electrically insulating material.
Claim 10
Dependent Claim
30 words
The wiring scheme of claim 1 or 5 wherein at least a portion of the first chip site first directional wiring line at the first chip site has been removed.
Claim 11
Dependent Claim
43 words
The wiring scheme of claim 1 or 5 further comprising at least one wiring interconnection line at the second chip site connecting one second chip site chip connection pad with the second chip site first directional wiring line at the second chip site.
Claim 12
Dependent Claim
48 words
The wiring scheme of claim 5 wherein one of the second chip site first directional wiring lines at the second chip site is an X wiring line and one of the second chip site second directional wiring lines at the second chip site is a Y wiring line.
Claim 13
Dependent Claim
30 words
The wiring scheme of claim 1 or 5 wherein at least a portion of the second chip site first directional wiring line at the second chip site has been removed.
Claim 14
Dependent Claim
30 words
The wiring scheme of claim 5 wherein at least a portion of one of the second chip site second directional wiring lines at the second chip site has been removed.
Claim 15
Dependent Claim
81 words
The wiring scheme of claim 5 wherein the overlapping second chip site second directional wiring lines at the second chip site jogs underneath the second chip site first directional wiring lines, such jog comprising a traverse down to a subsurface portion of the thin film layer through a via, a traverse across the subsurface portion and underneath the other of the overlapping directional wiring lines and a traverse up to the one of the overlapping directional wiring lines through another via.
Claim 16
Dependent Claim
295 words
A thin film wiring scheme on a substrate comprising: a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer; a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines,wherein the orthogonal directional wiring lines at the first chip site overlap but do not contact each other; at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site; a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces; a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines; at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site; and a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.
Claim 17
Dependent Claim
295 words
A thin film wiring scheme on a substrate comprising: a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer; a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines,wherein the orthogonal directional wiring lines at the first chip site overlap but do not contact each other; at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site; a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces; a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines; at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site; and a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.
Claim 18
Dependent Claim
79 words
The wiring scheme of claim 14 wherein one of the orthogonal directional wiring lines at the first chip site jogs underneath the other of the orthogonal directional wiring lines, such jog comprising a traverse down to a subsurface portion of the thin film layer through a via, a traverse across the subsurface portion and underneath the other of the orthogonal directional wiring lines and a traverse up to the one of the orthogonal directional wiring lines through a via.
Claim 19
Dependent Claim
296 words
A thin film wiring scheme on a substrate comprising: a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer; a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines; at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site; a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces; a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines, wherein the orthogonal directional wiring lines at the second chip site overlap but do not contact each other; at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site; and a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.
Claim 20
Dependent Claim
296 words
A thin film wiring scheme on a substrate comprising: a plurality of chip connection pads at a first chip site with an inter pad spacing on a thin film layer; a plurality of directional wiring lines interspersed between the first chip site chip connection pads, at least one of the first chip site directional wiring lines being orthogonal to at least another one of the first chip site directional wiring lines; at least one wiring interconnection line connecting one of the first chip site chip connection pads with one of the directional wiring lines at the first chip site; a plurality of chip connection pads at a second chip site with another inter pad spacing on the thin film layer, where the first chip site being separated from the second chip site by a space which is greater than any of said inter pad spaces; a plurality of directional wiring lines interspersed between the second chip site chip connection pads, at least one of the second chip site directional wiring lines being orthogonal to at least another one of the second chip site directional wiring lines, wherein the orthogonal directional wiring lines at the second chip site overlap but do not contact each other; at least one wiring interconnection line connecting one of the second chip site chip connection pads with one of the directional wiring lines at the second chip site; and a plurality of chip site interconnection lines connecting at least one of the directional wiring lines at the first chip site with at least one of the directional wiring lines at the second chip site, wherein the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines all being located on a single sublayer of the thin film layer.
Claim 21
Dependent Claim
36 words
The wiring scheme of claim 14 or 16 wherein all of the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines are on the top surface of the thin film layer.
Claim 22
Dependent Claim
36 words
The wiring scheme of claim 14 or 16 wherein all of the chip connection pads, directional wiring lines, wiring interconnection lines and chip site interconnection lines are covered with a protective layer of electrically insulating material.
Claim 23
Dependent Claim
28 words
The wiring scheme of claim 14 or 16 wherein at least a portion of one of the directional wiring lines at the first chip site has been removed.
Claim 24
Dependent Claim
79 words
The wiring scheme of claim 16 wherein one of the orthogonal directional wiring lines at the second chip site jogs underneath the other of the orthogonal directional wiring lines, such jog comprising a traverse down to a subsurface portion of the thin film layer through a via, a traverse across the subsurface portion and underneath the other of the orthogonal directional wiring lines and a traverse up to the one of the orthogonal directional wiring lines through a via.
Claim 25
Dependent Claim
28 words
The wiring scheme of claim 14 or 16 wherein at least a portion of one of the directional wiring lines at the second chip site has been removed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |