US6426260B1
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Switching speed improvement in DMO by implanting lightly doped region under gate
Assignee: CERLAN TECHNOLOGY VENTURES LLC
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Filing: 2000-09-05
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Granted: 2002-07-30
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Expires: 2020-09-05
Abstract
Abstract The preset invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide layer over the epi-layer; (b) depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) performing a high-energy body-conductivity-type-dopant implant, eg., boron implant, to form a plurality of shallow low-concentration regions of source-conductivity-type, e.g., n-regions, under each of e gates. A DMOS power device with improved switching speed is provided with reduced gate-to-drain capacitance without causing an increase in either the on-resistance of the threshold voltage.
Inventors
- 👤 Fwu-Iuan Hshieh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/0297; H10D30/668; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
133 words
A method for fabricating a DMOS transistor on a substrate comprising: (a) forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer; (b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates; (c) removing said polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; and (d) performing a high-energy light-dose body-conductivity-type dopant implant through said polysilicon gate to form a plurality of shallow low-concentration first-conductivity-type regions under each of said gates having a lower dopant concentration of said first conductivity type than said epitaxial layer.
Claim 2
Independent Claim
133 words
A method for fabricating a DMOS transistor on a substrate comprising: (a) forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer; (b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates; (c) removing said polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; and (d) performing a high-energy light-dose body-conductivity-type dopant implant through said polysilicon gate to form a plurality of shallow low-concentration first-conductivity-type regions under each of said gates having a lower dopant concentration of said first conductivity type than said epitaxial layer.
Claim 3
Dependent Claim
74 words
The method for fabricating said DMOS transistor of claim 1 further comprising: (e) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and performing a source diffusion process; and (f) forming an overlying insulation layer covering said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.
Claim 4
Dependent Claim
56 words
The method for fabricating said DMOS transistor of claim 1 further comprising a step of: (g) performing a low energy body-conductivity-type dopant implant to form a shallow high-concentration body-conductivity-type dopant region followed by applying a high temperature process for densification of said insulation layer and for activating a diffusion of said shallow high-concentration body-conductivity-type dopant regions.
Claim 5
Dependent Claim
82 words
The method for fabricating said MOSFET transistor of claim 1 wherein: said step (d) is a step of applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type; and said step (e) is a step of performing a high-energy light-dose second-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates followed by removing said source-blocking mask and performing a source diffusion process.
Claim 6
Dependent Claim
51 words
The method for fabricating said MOSFET transistor of claim 1 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.
Claim 7
Dependent Claim
51 words
The method for fabricating said MOSFET transistor of claim 3 wherein: said step (e) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.
Claim 8
Dependent Claim
62 words
The method for fabricating said MOSFET transistor of claim 1 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of implanting a plurality boron ions as second-conductivity-type dopant of said second conductivity type with an energy ranging from 200 to 400 Kev.
Claim 9
Dependent Claim
53 words
The method for fabricating said MOSFET transistor of claim 1 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions with a depth less than 0.4 micrometers.
Claim 10
Independent Claim
186 words
A method for fabricating a trench DMOS transistor on a substrate comprising steps of: (a) forming an epi-layer of a first conductivity type in said substrate with a bottom surface functioning as a drain; (b) performing a body implant of a second conductivity type followed by performing a body diffusion for forming a body regions; (c) applying a trench mask for etching a plurality of trenches in said substrate; (d) implanting a low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches; (e) depositing a polysilicon layer to fill said trenches and etching for removing said polysilicon layer from above said top surface of said substrate to form a plurality of trenched gates; (f) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and carrying out a source diffusion process; and (g) forming an overlying insulation layer covering said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.
Claim 11
Independent Claim
186 words
A method for fabricating a trench DMOS transistor on a substrate comprising steps of: (a) forming an epi-layer of a first conductivity type in said substrate with a bottom surface functioning as a drain; (b) performing a body implant of a second conductivity type followed by performing a body diffusion for forming a body regions; (c) applying a trench mask for etching a plurality of trenches in said substrate; (d) implanting a low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches; (e) depositing a polysilicon layer to fill said trenches and etching for removing said polysilicon layer from above said top surface of said substrate to form a plurality of trenched gates; (f) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and carrying out a source diffusion process; and (g) forming an overlying insulation layer covering said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.
Claim 12
Dependent Claim
39 words
The method for fabricating said trench DMOS transistor of claim 9 further comprising a step: (h) performing a high energy second-conductivity-type dopant implant to form a self-aligned deep high concentration second-conductivity-type dopant region below each of said source regions.
Claim 13
Dependent Claim
47 words
The method for fabricating said MOSFET transistor of claim 9 wherein: said step (d) of forming said plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of forming said shallow-and-narrow low-concentration source-dopant regions with a region-width narrower than each of said trenches.
Claim 14
Dependent Claim
59 words
The method for fabricating said trench DMOS transistor of claim 9 wherein: said step (d) of implanting said low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of implanting a plurality boron ions as second-conductivity-type dopant with an energy ranging from 20 to 80 Kev.
Claim 15
Dependent Claim
59 words
The method for fabricating said MOSFET transistor of claim 9 wherein: said step (d) of implanting said low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of forming said shallow-and-narrow low-concentration source-dopant regions with a depth less than 0.4 micrometers below each of said trenches.
Claim 16
Independent Claim
120 words
A method for fabricating a DMOS transistor on a substrate comprising: a)forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer; b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates; c) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type; and d) performing a high-energy light-dose second-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates followed by removing said source-blocking mask and performing a source diffusion process.
Claim 17
Independent Claim
120 words
A method for fabricating a DMOS transistor on a substrate comprising: a)forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer; b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates; c) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type; and d) performing a high-energy light-dose second-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates followed by removing said source-blocking mask and performing a source diffusion process.
Claim 18
Dependent Claim
39 words
The method for fabricating said DMOS transistor of claim 1 further comprising: e) forming an overlying insulation layer covering a top surface said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.
Claim 19
Dependent Claim
56 words
The method for fabricating said DMOS transistor of claim 15 further comprising a step of: f) performing a low energy body-conductivity-type dopant implant to form a shallow high-concentration body-conductivity-type dopant region followed by applying a high temperature process for densification of said insulation layer and for activating a diffusion of said shallow high-concentration body-conductivity-type dopant regions.
Claim 20
Dependent Claim
94 words
The method for fabricating said MOSFET transistor of claim 14 wherein: said step (c) is a step of removing said polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; and said step (d) is a step of performing a high-energy light-dose body-conductivity-type dopant implant through said polysilicon gate to form a plurality of shallow low-concentration first-conductivity-type regions under each of said gates having a lower dopant concentration of said fist conductivity type than said epitaxial layer.
Claim 21
Dependent Claim
51 words
The method for fabricating said MOSFET transistor of claim 14 wherein: said step (e) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.
Claim 22
Dependent Claim
51 words
The method for fabricating said MOSFET transistor of claim 17 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.
Claim 23
Dependent Claim
62 words
The method for fabricating said MOSFET transistor of claim 14 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of implanting a plurality boron ions as second-conductivity-type dopant of said second conductivity type with an energy ranging from 200 to 400 Kev.
Claim 24
Dependent Claim
53 words
The method for fabricating said MOSFET transistor of claim 14 wherein: said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions with a depth less than 0.4 micrometers.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-07-29 | 2006-01-28 | 2006-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-29 | 2010-01-28 | 2010-07-30 | $3760.00 | Window Closed / Lapsed |
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