US6025233A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device
Assignee: NGK Insulators Ltd
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Filing: 1999-05-20
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Granted: 2000-02-15
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Expires: 2019-05-20
Abstract
Abstract A vertical type semiconductor device having a semiconductor substrate and at least one gate electrode structure formed in the semiconductor substrate for controlling a current flow across the semiconductor substrate. The semiconductor substrate is formed by a silicon substrate, a silicon carbide or diamond layer epitaxially deposited on the silicon substrate, and a silicon layer epitaxially deposited on the silicon carbide or diamond layer. Recesses are formed in the silicon layer and gate electrodes are provided in the recesses via silicon oxide films. Source or emitter regions are formed in portions of the silicon layer which are brought into contact with the silicon oxide films by inverting the conductivity of these portions. Source or emitter electrodes are provided on the source or emitter regions, and a drain or collector electrode is provided on a rear surface of the silicon substrate.
Inventors
- 👤 Yoshio Terasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D12/00; H10D12/01; H10D12/031; H10D12/411; H10D12/441; H10D12/461; H10D12/481; H10D30/01; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/152; H10D62/154; H10D62/80; H10D62/83; H10D62/8303; H10D62/832; H10D62/8325; H10D62/82; H10D62/822; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; Y; Y10; Y10S; Y10S438/00; Y10S438/931
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
220 words
A method of manufacturing a semiconductor device comprising the steps of: preparing a silicon substrate having first and second major surfaces and a first impurity concentration; epitaxially growing, on the second surface of the silicon substrate, a semiconductor material having a band-gap wider than the silicon substrate to form a wide band-gap semiconductor material layer, said wide band-gap semiconductor material layer having a second impurity concentration lower than said first impurity concentration of the silicon substrate; epitaxially growing a silicon layer on said wide band-gap semiconductor material layer, said silicon layer having a third impurity concentration higher than said second impurity concentration of the wide band-gap semiconductor material layer; forming at least one recess at least in said silicon layer by anisotropic etching; forming at least one silicon oxide film on an inner wall of said at least one recess; forming at least one gate electrode on said at least one silicon oxide film; forming at least one source or emitter region in a surface of the silicon layer by inverting the conductivity type of a portion of the silicon layer which adjoins the silicon oxide film; forming at least one source or emitter electrode on said at least one source or emitter region; and forming a drain or collector electrode on said first major surface of the silicon substrate.
Claim 2
Independent Claim
220 words
A method of manufacturing a semiconductor device comprising the steps of: preparing a silicon substrate having first and second major surfaces and a first impurity concentration; epitaxially growing, on the second surface of the silicon substrate, a semiconductor material having a band-gap wider than the silicon substrate to form a wide band-gap semiconductor material layer, said wide band-gap semiconductor material layer having a second impurity concentration lower than said first impurity concentration of the silicon substrate; epitaxially growing a silicon layer on said wide band-gap semiconductor material layer, said silicon layer having a third impurity concentration higher than said second impurity concentration of the wide band-gap semiconductor material layer; forming at least one recess at least in said silicon layer by anisotropic etching; forming at least one silicon oxide film on an inner wall of said at least one recess; forming at least one gate electrode on said at least one silicon oxide film; forming at least one source or emitter region in a surface of the silicon layer by inverting the conductivity type of a portion of the silicon layer which adjoins the silicon oxide film; forming at least one source or emitter electrode on said at least one source or emitter region; and forming a drain or collector electrode on said first major surface of the silicon substrate.
Claim 3
Dependent Claim
27 words
A method according to claim 1, wherein said at least one recess is formed such that the recess partially penetrates into the wide band-gap semiconductor material layer.
Claim 4
Dependent Claim
34 words
A method according to claim 1, wherein said at least one recess is formed such that a surface of said wide band-gap semiconductor material layer is just exposed at a bottom of the recess.
Claim 5
Dependent Claim
57 words
A method according to claim 1, wherein said at least one recess is formed within said silicon layer such that a distance between a bottom of the recess and a surface of the wide band-gap semiconductor material layer is equal to a depth of an inversion channel formed in the silicon layer during operation of semiconductor device.
Claim 6
Dependent Claim
65 words
A method according to claim 1, wherein after forming said wide band-gap semiconductor layer, impurity ions are diffused from the silicon substrate into the wide band-gap semiconductor material layer to form a diffusion layer in a surface of the wide band-gap semiconductor material layer, said diffusion layer having an impurity concentration lower than the silicon substrate, but higher than the wide band-gap semiconductor material layer.
Claim 7
Dependent Claim
49 words
A method according to claim 1, wherein after forming the silicon layer on the wide band-gap semiconductor material layer, impurity ions are diffused from the silicon layer into the wide-band gap semiconductor material layer to form a diffusion layer in a surface of the wide band-gap semiconductor material layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |