Patent US6426257B1 successfully refreshed from Google Patents.
US6426257B1
Expired / Lapsed
US
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Flash memory and manufacturing method therefor
Assignee: NEC Electronics Corp
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Filing: 2000-04-19
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Granted: 2002-07-30
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Expires: 2020-04-19
Abstract
Abstract In a flash memory that has a floating gate, a control gate, and an erase gate that are all mutually insulated, in which data erasing is performed by extracting electrons from the corner edge of the floating gate to the erase gate via an insulation film, the insulation film between the floating gate and the erase gate is formed so as to have a uniform thickness at its corner part.
Inventors
- 👤 Kohji Kanamori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:22
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10D; H10D30/00; H10D30/60; H10D30/68; H10B69/00; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of: forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate; forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and forming a silicon thermal oxide film after said forming of said silicon oxide layer on said floating gate using a CVD process.
Claim 2
Independent Claim
139 words
A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of: forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate; forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and forming a silicon thermal oxide film after said forming of said silicon oxide layer on said floating gate using a CVD process.
Claim 3
Dependent Claim
46 words
A method of manufacturing a flash memory according to claim 1 , further comprising a step of performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said step of forming a silicon oxide layer on the floating gate, using a CVD process.
Claim 4
Dependent Claim
25 words
The method of claim 1 , wherein said corner surface is a curved part having a uniform thickness at a corner of said floating gate.
Claim 5
Dependent Claim
19 words
The method of claim 3 , wherein said curved part is at a uniform distance from said floating gate.
Claim 6
Independent Claim
145 words
A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of: forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate; forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said forming of said silicon oxide film on said floating gate using a CVD process.
Claim 7
Independent Claim
145 words
A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of: forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate; forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said forming of said silicon oxide film on said floating gate using a CVD process.
Claim 8
Dependent Claim
29 words
The method of claim 5 , wherein said silicon oxide layer at said corner surface forms a curved part that is at a uniform distance from said floating gate.
Claim 9
Dependent Claim
37 words
The method of claim 6 , wherein said curved part has a top portion opposite said floating gate approximating a quarter circle having a center which is a corner of said floating gate opposite said top portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-29 | 2006-01-28 | 2006-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-29 | 2010-01-28 | 2010-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-29 | 2014-01-28 | 2014-07-30 | $7700.00 | Window Closed / Lapsed |