Method of manufacturing non-volatile semiconductor memory having erasing gate

Claim 1

A method of manufacturing a semiconductor memory device including a memory cell transistor and a peripheral transistor, comprising the steps of: forming a floating gate and a control gate of said memory cell transistor on a first region of a semiconductor substrate; covering said floating gate and said control gate with a first insulating layer, said first insulating layer having a first portion which is formed on one part of a peripheral portion of said floating gate and serves as a tunneling insulating film, a second portion which is formed on a remaining part of said peripheral portion of said floating gate, and a third portion which is formed on a top surface of said control gate; forming a gate electrode of said peripheral transistor on a second region of said semiconductor substrate separate from said first region; covering said gate electrode with a second insulating layer; depositing a conductive layer to cover said first and second insulating layers; etching back said conductive layer until said third portion of said first insulating film and said second insulating layer are exposed, a first part of said conductive layer being thereby left on said first portion of said first insulating layer to serve as an erasing gate of said memory cell transistor and a second part of said conductive layer being left on said second portion of said first insulating layer; forming a first mask layer on said second insulating layer to protect said peripheral transistor and a second mask layer on said first part of said conductive layer to protect said erasing gate; and removing said second part of said conductive layer by use of said first and second mask layers as a mask.

Claim 2

A method of manufacturing a semiconductor memory device including a memory cell transistor and a peripheral transistor, comprising the steps of: forming a floating gate and a control gate of said memory cell transistor on a first region of a semiconductor substrate; covering said floating gate and said control gate with a first insulating layer, said first insulating layer having a first portion which is formed on one part of a peripheral portion of said floating gate and serves as a tunneling insulating film, a second portion which is formed on a remaining part of said peripheral portion of said floating gate, and a third portion which is formed on a top surface of said control gate; forming a gate electrode of said peripheral transistor on a second region of said semiconductor substrate separate from said first region; covering said gate electrode with a second insulating layer; depositing a conductive layer to cover said first and second insulating layers; etching back said conductive layer until said third portion of said first insulating film and said second insulating layer are exposed, a first part of said conductive layer being thereby left on said first portion of said first insulating layer to serve as an erasing gate of said memory cell transistor and a second part of said conductive layer being left on said second portion of said first insulating layer; forming a first mask layer on said second insulating layer to protect said peripheral transistor and a second mask layer on said first part of said conductive layer to protect said erasing gate; and removing said second part of said conductive layer by use of said first and second mask layers as a mask.

Claim 3

A method of a semiconductor memory device comprising the steps of: selectively forming a first conductive layer on a first insulating layer covering a semiconductor substrate; covering said first conductive layer with a second insulating layer; forming first and second control gates on said second insulating layer separately from each other; covering said first and second control gates with third and fourth insulating layers, respectively; selectively removing said first conductive layer by use of said third and fourth insulating layers as a mask to form first and second floating gates, each of said first and second floating gates thereby having an exposed side surface; forming first and second tunnel insulating films on the exposed side surfaces of said first and second floating gates, respectively; forming a second conductive layer to cover said first to fourth insulating layers and to fill a space between said first and second tunnel insulating films; etching back said second conductive layer until top surfaces of said third and fourth insulating layers are exposed, a first part of said second conductive layer being thereby left in contact with said first and second tunnel insulating films to serve as a erasing gate and a second part of said second conductive layer being left in contact with said second insulating film covering said erasing gate with a mask layer; and removing said second part of said second conductive layer by use of said mask layer as a mask.

Claim 4

A method of a semiconductor memory device comprising the steps of: selectively forming a first conductive layer on a first insulating layer covering a semiconductor substrate; covering said first conductive layer with a second insulating layer; forming first and second control gates on said second insulating layer separately from each other; covering said first and second control gates with third and fourth insulating layers, respectively; selectively removing said first conductive layer by use of said third and fourth insulating layers as a mask to form first and second floating gates, each of said first and second floating gates thereby having an exposed side surface; forming first and second tunnel insulating films on the exposed side surfaces of said first and second floating gates, respectively; forming a second conductive layer to cover said first to fourth insulating layers and to fill a space between said first and second tunnel insulating films; etching back said second conductive layer until top surfaces of said third and fourth insulating layers are exposed, a first part of said second conductive layer being thereby left in contact with said first and second tunnel insulating films to serve as a erasing gate and a second part of said second conductive layer being left in contact with said second insulating film covering said erasing gate with a mask layer; and removing said second part of said second conductive layer by use of said mask layer as a mask.

Claim 6

A method of manufacturing a non-volatile semiconductor memory, comprising the steps of; forming a floating gate on a first region of a semiconductor substrate having said first region and a second region, forming a dielectric film on said floating gate, forming a first conductive film on the entire surface of said first region and said second region, selectively etching said first conductive film thereby to form a gate of a transistor over said second region and a control gate over said dielectric film, forming said walls on both sides of said control gate, forming a tunnel dielectric film adjacent to said floating gate, forming a second conductive film on the entire surface of said first region and said second region, etching back said second conductive film by an amount almost equal to the thickness of said second conductive film to remove said second conductive film from said second region and make an erasing gate adjacent to said tunnel dielectric film, covering said erasing gate and said transistor with a mask, and removing said second conductive film remaining in the regions outside said mask.

Claim 7

A method of manufacturing a non-volatile semiconductor memory, comprising the steps of; forming a floating gate on a first region of a semiconductor substrate having said first region and a second region, forming a dielectric film on said floating gate, forming a first conductive film on the entire surface of said first region and said second region, selectively etching said first conductive film thereby to form a gate of a transistor over said second region and a control gate over said dielectric film, forming said walls on both sides of said control gate, forming a tunnel dielectric film adjacent to said floating gate, forming a second conductive film on the entire surface of said first region and said second region, etching back said second conductive film by an amount almost equal to the thickness of said second conductive film to remove said second conductive film from said second region and make an erasing gate adjacent to said tunnel dielectric film, covering said erasing gate and said transistor with a mask, and removing said second conductive film remaining in the regions outside said mask.