Semiconductor device having an impurity region overlapping a gate electrode

Claim 2

A semiconductor device having a first semiconductor element and a second semiconductor element, said first semiconductor element comprising: a first semiconductor film formed over a substrate on an insulating surface; a first gate electrode adjacent to said first semiconductor film with a gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said gate electrode; a channel region formed in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region formed in said first semicondutor and overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed therebetween; and a second semiconductor element comprising: a second semiconductor film formed over the substrate having the insulating surface; a third gate electrode adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity in said second semiconductor film not overlapping with said third gate electrode.

Claim 3

A semiconductor device having a high voltage circuit consisting of a first semiconductor element and a high speed drive circuit consisting of a second semiconductor element formed over a same substrate having an insulating surface, said first semiconductor element comprising: a first semiconductor film formed over a substrate having an insulating surface; a first gate electrode adjacent to said first semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate insulating film and being in contact with said gate insulating film; a channel region in said semiconductor film and overlapping with the region in contact with said gate insulating film of first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate electrode interposed therebetween; and said second semiconductor element comprising: a second semiconductor film formed over the substrate having the insulating surface; a third gate electrode adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 4

A semiconductor device having a high voltage circuit consisting of a first semiconductor element and a high speed drive circuit consisting of a second semiconductor element formed over a same substrate having an insulating surface, said first semiconductor element comprising: a first semiconductor film formed over a substrate having an insulating surface; a first gate electrode adjacent to said first semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate insulating film and being in contact with said gate insulating film; a channel region in said semiconductor film and overlapping with the region in contact with said gate insulating film of first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate electrode interposed therebetween; and said second semiconductor element comprising: a second semiconductor film formed over the substrate having the insulating surface; a third gate electrode adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 5

A semiconductor device having pixels each consisting of an n-channel type thin film transistor and CMOS circuits each consisting of an n-channel type thin film transistor and a p-channel type thin film transistor, said n-channel type thin film transistor of said pixels comprising: a first semiconductor film formed over a substrate having an insulating surface; a first gate electrode formed adjacent to said first semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said gate insulating film a channel region formed in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed therebetween; and said n-channel type thin film transistor of said CMOS circuit comprising: a second semiconductor film formed over the substrate having on the insulating surface; a third gate electrode formed adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 6

A semiconductor device having pixels each consisting of an n-channel type thin film transistor and CMOS circuits each consisting of an n-channel type thin film transistor and a p-channel type thin film transistor, said n-channel type thin film transistor of said pixels comprising: a first semiconductor film formed over a substrate having an insulating surface; a first gate electrode formed adjacent to said first semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said gate insulating film a channel region formed in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed therebetween; and said n-channel type thin film transistor of said CMOS circuit comprising: a second semiconductor film formed over the substrate having on the insulating surface; a third gate electrode formed adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 7

A semiconductor device according to claim 1 , wherein said second semiconductor element does not have a gate electrode covering said third gate electrode.

Claim 8

A semiconductor device according to claim 1 , wherein said impurity region is in contact with said channel region.

Claim 9

A semiconductor device according to claim 1 , wherein said impurity region contains an impurity element of Group 15 in a concentration of 1×10 16 to 1×10 19 atms/cm 3 .

Claim 10

A semiconductor device according to claim 2 , wherein said second semiconductor element does not have a gate electrode covering said third gate electrode.

Claim 11

A semiconductor device according to claim 2 , wherein said impurity region is in contact with said channel region.

Claim 12

A semiconductor device according to claim 2 , wherein said impurity region contains an impurity element of Group 15 in a concentration of 1×10 16 to 1×10 19 atms/cm 3 .

Claim 13

A semiconductor device according to claim 3 , wherein said second semiconductor element does not have a gate electrode covering said third gate electrode.

Claim 14

A semiconductor device according to claim 3 , wherein said impurity region is in contact with said channel region.

Claim 15

A semiconductor device according to claim 3 , wherein said impurity region contains an impurity element of Group 15 in a concentration of 1×10 16 to 1×10 19 atms/cm 3 .

Claim 16

A semiconductor device having CMOS circuits each consisting of an n-channel type thin film transistor and a p-channel type thin film transistor, said n-channel type thin film transistor comprising: a semiconductor film formed over a substrate having an insulating surface; a first gate electrode formed adjacent to said semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said is gate insulating film; a channel region in said semiconductor film overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region in said semiconductor film overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating film interposed therebetween; and said p-channel type thin film transistor comprising: a third gate electrode formed adjacent to said semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 17

A semiconductor device having CMOS circuits each consisting of an n-channel type thin film transistor and a p-channel type thin film transistor, said n-channel type thin film transistor comprising: a semiconductor film formed over a substrate having an insulating surface; a first gate electrode formed adjacent to said semiconductor film with said gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said is gate insulating film; a channel region in said semiconductor film overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region in said semiconductor film overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating film interposed therebetween; and said p-channel type thin film transistor comprising: a third gate electrode formed adjacent to said semiconductor film with said gate insulating film interposed therebetween; at least one impurity region in said second semiconductor film not overlapping with said third gate electrode.

Claim 18

A semiconductor device according to claim 13 , wherein said second semiconductor element does not have a gate electrode covering said third gate electrode.

Claim 19

A semiconductor device according to claim 13 , wherein said impurity region is in contact with said channel region.

Claim 20

A semiconductor device according to claim 13 , wherein said impurity region contains an impurity element of Group 15 in a concentration of 1×10 16 to 1×10 19 atms/cm 3 .

Claim 21

A semiconductor device according to claim 1 , wherein said first gate electrode or said third gate electrode is a single layer or multiple layer of a metal or an alloy thereof selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), aluminum (Al), and copper (Cu).

Claim 22

A semiconductor device according to claim 1 , wherein the material of said second gate electrode is different from that of said first gate electrode.

Claim 23

A semiconductor device according to claim 2 , wherein said first gate electrode or said third gate electrode is a single layer or multiple layer of a metal or an alloy thereof selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), aluminum (Al), and copper (Cu).

Claim 24

A semiconductor device according to claim 2 , wherein the material of said second gate electrode is different from that of said first gate electrode.

Claim 25

A semiconductor device according to claim 3 , wherein said first gate electrode or said third gate electrode is a single layer or multiple layer of a metal or an alloy thereof selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), aluminum (Al), and copper (Cu).

Claim 26

A semiconductor device according to claim 3 , wherein the material of said second gate electrode is different from that of said first gate electrode.

Claim 27

A semiconductor device according to claim 13 , wherein said first gate electrode or said third gate electrode is a single layer or multiple layer of a metal or an alloy thereof selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), aluminum (Al), and copper (Cu).

Claim 28

A semiconductor device according to claim 13 , wherein the material of said second gate electrode is different from that of said first gate electrode.

Claim 29

A semiconductor device according to claim 1 , wherein said semiconductor device is a display device using an organic electroluminescence material.

Claim 30

A semiconductor device according to claim 1 , wherein said semiconductor device is incorporated into an electric equipment selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital versatile disk player, a goggle type display, and a projector.

Claim 31

A semiconductor device according to claim 2 , wherein said semiconductor device is a display device using an organic electroluminescence material.

Claim 32

A semiconductor device according to claim 2 , wherein said semiconductor device is incorporated into an electric equipment selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital versatile disk player, a goggle type display, and a projector.

Claim 33

A semiconductor device according to claim 3 , wherein said semiconductor device is a display device using an organic electroluminescence material.

Claim 34

A semiconductor device according to claim 3 , wherein said semiconductor device is incorporated into an electric equipment selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital versatile disk player, a goggle type display, and a projector.

Claim 35

A semiconductor device according to claim 13 , wherein said semiconductor device is a display device using an organic electroluminescence material.

Claim 36

A semiconductor device according to claim 13 , wherein said semiconductor device is incorporated into an electric equipment selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital versatile disk player, a goggle type display, and a projector.

Claim 37

An electroluminescence display device comprising: a pixel portion and a peripheral driving circuit portion formed over a substrate having an insulating surface; at least a first thin film transistor for controlling current and a second thin film transistor for switching each being formed in the pixel portion; at least a CMOS transistor formed in the peripheral driving circuit portion; wherein said first thin film transistor includes: a first semiconductor film formed over the substrate; a first gate electrode adjacent to said first semiconductor film with a gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said gate electrode; a channel region formed in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region formed in said first impurity region and overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed therebetween; a pixel electrode being electrically connected to said impurity region of said first thin film transistor, wherein said second thin film transistor comprising: a second semiconductor film formed over the substrate; a third gate electrode adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity in said second semiconductor film not overlapping with said third gate electrode, and a light emitting layer being formed over the pixel electrode, an electrode being formed over the light emitting layer.

Claim 38

An electroluminescence display device comprising: a pixel portion and a peripheral driving circuit portion formed over a substrate having an insulating surface; at least a first thin film transistor for controlling current and a second thin film transistor for switching each being formed in the pixel portion; at least a CMOS transistor formed in the peripheral driving circuit portion; wherein said first thin film transistor includes: a first semiconductor film formed over the substrate; a first gate electrode adjacent to said first semiconductor film with a gate insulating film interposed therebetween; a second gate electrode covering said first gate electrode and being in contact with said gate electrode; a channel region formed in said first semiconductor film and overlapping with the region in contact with said gate insulating film of said first gate electrode, with said gate insulating film interposed therebetween; at least one impurity region formed in said first impurity region and overlapping with the region in contact with said gate insulating film of said second gate electrode, with said gate insulating interposed therebetween; a pixel electrode being electrically connected to said impurity region of said first thin film transistor, wherein said second thin film transistor comprising: a second semiconductor film formed over the substrate; a third gate electrode adjacent to said second semiconductor film with said gate insulating film interposed therebetween; at least one impurity in said second semiconductor film not overlapping with said third gate electrode, and a light emitting layer being formed over the pixel electrode, an electrode being formed over the light emitting layer.

Claim 39

An electroluminescence display device according to claim 33 wherein said light emitting layer is an EL layer.

Claim 40

An electroluminescence display device according to claim 33 , wherein at least one of the pixel electrode and the electrode is transparent.

Claim 41

An electroluminescence display device according to claim 33 , wherein said electroluminescence display device is incorporated into an electric equipment selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital versatile disk player, a goggle type display, and a projector.