Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith

Claim 2

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulatling surface, said semiconductor film having a channel region with first and second sides and a pair of impurity regions on both sides of said channel region; at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminated on said gate insulating film, a second conductive layer, and a third conductive layer, wherein said pair of impurity regions partially overlaps said gate electrode with said gate insulating film interposed therebetween; and wherein said second conductive layer comprises aluminum.

Claim 3

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having a channel region, a first impurity region, a second impurity region, and a third impurity region; at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminated on said gate insulating film, a second conductive layer, and a third conductive layer, wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate electrode with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and does not overlap said gate electrode with said gate insulating film interposed therebetween, and wherein said second conductive layer comprises aluminum.

Claim 4

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having a channel region, a first impurity region, a second impurity region, and a third impurity region; at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminated on said gate insulating film, a second conductive layer, and a third conductive layer, wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate electrode with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and does not overlap said gate electrode with said gate insulating film interposed therebetween, and wherein said second conductive layer comprises aluminum.

Claim 5

A semiconductor device comprising: at least one CMOS circuit having an n-channel type thin film transistor and a p-channel type thin film transistor; at least one gate wiring adjacent to each of semiconductor films of said n-channel type and p-channel type thin film transistors with a gate insulating film interposed therebetween, said gate wiring being formed of a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on said gate insulating film, wherein said semiconductor film of said n-channel type thin film transistor comprises a channel region, a first impurity region, a second impurity region, and a third impurity region; wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate wiring with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and does not overlap said gate wiring with said gate insulating film interposed therebetween; and wherein said second conductive layer comprises aluminum.

Claim 6

A semiconductor device comprising: at least one CMOS circuit having an n-channel type thin film transistor and a p-channel type thin film transistor; at least one gate wiring adjacent to each of semiconductor films of said n-channel type and p-channel type thin film transistors with a gate insulating film interposed therebetween, said gate wiring being formed of a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on said gate insulating film, wherein said semiconductor film of said n-channel type thin film transistor comprises a channel region, a first impurity region, a second impurity region, and a third impurity region; wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate wiring with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and does not overlap said gate wiring with said gate insulating film interposed therebetween; and wherein said second conductive layer comprises aluminum.

Claim 7

A semiconductor device according to claim 3 , wherein said semiconductor film of said p-channel type thin film transistor has a channel region and a p-type impurity region which is adjacent to said channel region and does not overlap said gate wiring.

Claim 8

A semiconductor device according to claims 1 to 3 , wherein said first conductive layer comprises tantalum.

Claim 9

A semiconductor device according to claims 1 to 3 , wherein said first and second conductive layers have side surfaces and said third conductive surface has top and side surfaces and an anodic oxide layer is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 10

A semiconductor device according to claims 1 to 3 , wherein said third conductive layer is comprises tantalum.

Claim 11

A semiconductor device according to claims 1 to 3 , wherein said semiconductor device is an active matrix type display device.

Claim 12

A semiconductor device according to claims 1 to 3 , wherein said semiconductor device is an electronic device selected from the group consisting of a video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer, or a personal digital assistant.

Claim 13

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having two-sided channel region and a pair of impurity regions on both sides of said channel region; and at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminated on said gate insulating film, a second conductive layer, and a third conductive layer, wherein said pair of impurity regions partially overlaps said gate electrode with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces and an anodic oxide layer of said gate electrode is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 14

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having two-sided channel region and a pair of impurity regions on both sides of said channel region; and at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminated on said gate insulating film, a second conductive layer, and a third conductive layer, wherein said pair of impurity regions partially overlaps said gate electrode with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces and an anodic oxide layer of said gate electrode is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 15

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having a channel region, a first impurity region, a second impurity region, and a third impurity region; and at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminiated on said gate insulating film, second conductive layer, and a third conductive layer, wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate electrode with said gate insulating film interposed therebetween, wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and doesn overlap said gate electrode with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces, and an anodic oxide layer of said gate electrode is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 16

A semiconductor device having at least one thin film transistor, said thin film transistor comprising: a semiconductor film over a substrate having an insulating surface, said semiconductor film having a channel region, a first impurity region, a second impurity region, and a third impurity region; and at least one gate electrode adjacent to said semiconductor film with a gate insulating film interposed therebetween, said gate electrode being formed of a multilayer film including in consequence a first conductive layer laminiated on said gate insulating film, second conductive layer, and a third conductive layer, wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate electrode with said gate insulating film interposed therebetween, wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and doesn overlap said gate electrode with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces, and an anodic oxide layer of said gate electrode is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 17

A semiconductor device comprising: at least one CMOS circuit having an n-channel type thin film transistor and a p-channel type thin film transistor; and at least one gate wiring adjacent to each of semiconductor films of said n-channel type and p-channel type thin film transistors with a gate insulating film interposed therebetween, said gate wiring being formed of a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on said gate insulating film, wherein said semiconductor film of said n-channel type thin film transistor comprises a channel region, a first impurity region, a second impurity region, a third impurity region; wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate wiring with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and doesn overlap said gate wiring with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces, and an anodic oxide layer of said gate wiring is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 18

A semiconductor device comprising: at least one CMOS circuit having an n-channel type thin film transistor and a p-channel type thin film transistor; and at least one gate wiring adjacent to each of semiconductor films of said n-channel type and p-channel type thin film transistors with a gate insulating film interposed therebetween, said gate wiring being formed of a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on said gate insulating film, wherein said semiconductor film of said n-channel type thin film transistor comprises a channel region, a first impurity region, a second impurity region, a third impurity region; wherein said second impurity region is sandwiched between said first impurity region and said channel region, and overlaps said gate wiring with said gate insulating film interposed therebetween; wherein said third impurity region is sandwiched between said first impurity region and said second impurity region and doesn overlap said gate wiring with said gate insulating film interposed therebetween, and wherein said first and second conductive layers have side surfaces and said third conductive layer has top and side surfaces, and an anodic oxide layer of said gate wiring is formed on the side surfaces of said first and second conductive layers and on the top and side surfaces of said third conductive layer.

Claim 19

A semiconductor device according to claim 12 , wherein said semiconductor film of said p-channel type thin film transistor has a channel region and a p-type impurity region which is adjacent to said channel region and does not overlap said gate wiring.

Claim 20

A semiconductor device according to claims 10 to 12 , wherein said first conductive layer comprises tantalum.

Claim 21

A semiconductor device according to claims 10 to 12 , wherein said second conductive layer comprises aluminum.

Claim 22

A semiconductor device according to claims 10 to 12 , wherein said third conductive layer comprises tantalum.

Claim 23

A semiconductor device according to claims 10 to 12 , wherein said semiconductor device is an active matrix type display device.

Claim 24

A semiconductor device according to claims 10 to 12 , wherein said semiconductor device is an electronic device selected from the group consisting of a video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer, or a personal digital assistant.