Semiconductor device and method of fabricating the same

Claim 1

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing thermal layer being made of silicon, InP, diamond or BP; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T and higher than the second thermal expansion coefficient T 2 .

Claim 2

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing thermal layer being made of silicon, InP, diamond or BP; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T and higher than the second thermal expansion coefficient T 2 .

Claim 5

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is lower than a ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is higher than the ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 6

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is lower than a ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is higher than the ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 7

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing thermal layer being made of ZnO, GaAs, MgO, MgAlO 2 or BeO; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 .

Claim 8

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing thermal layer being made of ZnO, GaAs, MgO, MgAlO 2 or BeO; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 .

Claim 9

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is lower than a ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is higher than the ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 10

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; and forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1), the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is lower than a ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is higher than the ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 11

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing layer being made of silicon, InP, diamond or BP; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 .

Claim 12

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing layer being made of silicon, InP, diamond or BP; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 .

Claim 16

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is lower than a ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is higher than the ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 17

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being lower than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being lower than the first thermal expansion coefficient T 1 and higher than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is lower than a ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 1 /T 3 of the first thermal expansion coefficient T 1 to the third thermal expansion coefficient T 3 is higher than the ratio T 3 /T 2 of the third thermal expansion coefficient T 3 to the second thermal expansion coefficient T 2 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 18

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing layer being made of ZnO, GaAs, MgO, MgAlO 2 or BeO; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 .

Claim 19

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 , said strain reducing layer being made of ZnO, GaAs, MgO, MgAlO 2 or BeO; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 .

Claim 20

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 3 /T 1 of the first thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is lower than a ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is higher than the ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.

Claim 21

A method of fabricating a semiconductor device, the method comprising the steps of: forming a strain reducing layer having a second thermal expansion coefficient T 2 on a substrate having a first thermal expansion coefficient T 1 ; forming a semiconductor layer having a third thermal expansion coefficient T 3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by Al Al y Ga 1−y−z In z N (0≦y≦1, 0≦z≦1); and separating the nitride compound semiconductor layer from a multilayer structure composed of the substrate and the strain reducing layer to form a semiconductor substrate composed of the nitride compound semiconductor layer, the second thermal expansion coefficient T 2 being higher than the first thermal expansion coefficient T 1 , the third thermal expansion coefficient T 3 being higher than the first thermal expansion coefficient T 1 and lower than the second thermal expansion coefficient T 2 , wherein the step of forming the strain reducing layer includes the step of forming, when a ratio T 3 /T 1 of the first thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is lower than a ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is smaller in thickness than the substrate and forming, when the ratio T 3 /T 1 of the third thermal expansion coefficient T 3 to the first thermal expansion coefficient T 1 is higher than the ratio T 2 /T 3 of the second thermal expansion coefficient T 2 to the third thermal expansion coefficient T 3 , the strain reducing layer such that the strain reducing layer is larger in thickness than the substrate.