Semiconductor integrated structure

Abstract

Abstract Translated from Japanese (57)【要約】 【課題】 接着層を用いる方法により母基板上に半導体 素子を集積する際に、高温下の接着により半導体素子層 に導入される歪みを低減し、および半導体の放熱を良好 に保つ半導体集積構造体の提供。 【解決手段】 母基板、歪み低減層、接着層、および半 導体素子層をこの順序に集積した構造体であって、その 歪み低減層が、その半導体素子層の０．６倍以上１．５ 倍以下の熱膨張係数、およびその母基板の２．５倍以上 のヤング率を有し、およびその接着層が高温硬化の性質 を有して、その接着層の上下の層を機械的に接着する機 能を持つことを特徴とする半導体集積構造体。 (57) Abstract: When a semiconductor element is integrated on a mother substrate by a method using an adhesive layer, distortion introduced into the semiconductor element layer due to bonding under high temperature is reduced, and heat dissipation of the semiconductor is improved. Providing semiconductor integrated structures to be maintained. A structure in which a mother substrate, a strain reducing layer, an adhesive layer, and a semiconductor element layer are integrated in this order, wherein the strain reducing layer is at least 0.6 times and 1.5 times as large as the semiconductor element layer. Has a coefficient of thermal expansion of less than twice, and a Young's modulus of 2.5 times or more that of the motherboard, and has a property of high-temperature curing, and mechanically bonds the layers above and below the adhesive layer. A semiconductor integrated structure characterized by having a function to perform.

Inventors

• 👤 Tatsushi Nakahara
• 👤 達志 中原
• 👤 Hiroyuki Tsuda
• 👤 裕之 津田
• 👤 Chikara Amano
• 👤 主税 天野

Bibliographic Details