US6413809B2
Expired / Lapsed
US
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Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench
Assignee: Toshiba Corp
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Filing: 2001-03-08
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Granted: 2002-07-02
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Expires: 2021-03-08
Abstract
Abstract A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
Inventors
- 👤 Takuya Nakamura
- 👤 Naoki Koido
- 👤 Hirohisa Iizuka
- 👤 Kazuhito Narita
- 👤 Seiichi Aritome
- 👤 Fumitaka Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:15
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A method of manufacturing a semiconductor device, comprising the steps of: sequentially depositing a first gate electrode and a mask layer on a semiconductor substrate through a gate insulation film; forming a trench in an element isolation region by etching said gate electrode, said gate insulation film and said semiconductor substrate in sequence by anisotropic etching; filling an element isolation insulation film in said trench substantially flush with said mask layer, with said mask layer remaining left; removing at least a part of said mask layer in a layer thicknesswise direction thereof, and thereafter recessing an upper edge corner of said element isolation insulation film by isotropic etching; and removing said mask layer and thereafter forming a second gate electrode by patterning said second gate electrode.
Claim 2
Independent Claim
126 words
A method of manufacturing a semiconductor device, comprising the steps of: sequentially depositing a first gate electrode and a mask layer on a semiconductor substrate through a gate insulation film; forming a trench in an element isolation region by etching said gate electrode, said gate insulation film and said semiconductor substrate in sequence by anisotropic etching; filling an element isolation insulation film in said trench substantially flush with said mask layer, with said mask layer remaining left; removing at least a part of said mask layer in a layer thicknesswise direction thereof, and thereafter recessing an upper edge corner of said element isolation insulation film by isotropic etching; and removing said mask layer and thereafter forming a second gate electrode by patterning said second gate electrode.
Claim 3
Dependent Claim
100 words
The semiconductor device manufacturing method according to claim 1 , wherein each of said first and second gate electrode is a floating gate electrode of a non-volatile memory transistor on which a control gate electrode is stacked, and said first gate electrode patterning step involves, after said step of recessing the upper edge corner of said element isolation insulation film by the isotropic etching, consecutively executing a step of depositing said control gate electrode on said first gate electrode through an inter-layer gate insulation film and a step of forming said control gate electrode by patterning said control gate electrode.
Claim 4
Dependent Claim
53 words
The semiconductor device manufacturing method according to claim 1 , wherein said step of recessing the upper edge corner of said element isolation insulation film by the isotropic etching is carried out to attain such a state that the recessed upper edge corner terminates at a side surface of said first gate electrode.
Claim 5
Independent Claim
226 words
A method of manufacturing a semiconductor device having a memory cell array in which non-volatile memory transistors each including a floating gate electrode and a control gate electrode coupled in capacity thereto are formed in array, said method comprising the steps of: sequentially depositing a first gate electrode and a mask layer on a semiconductor substrate through a gate insulation film; forming a trench in an element isolation region by etching said first gate electrode, said gate insulation film and said semiconductor substrate in sequence by anisotropic etching; filling an element isolation insulation film in said trench substantially flush with said mask layer, with said mask layer remaining left; removing at least a part of said mask layer in a layer thicknesswise direction thereof, and thereafter recessing an upper edge corner of said element isolation insulation film by isotropic etching; a step of removing said mask layer, and thereafter depositing a second gate electrode composing said floating gate electrode together with said first gate electrode; forming a slit for isolating said second gate electrode in said element isolation insulation film; a step of providing said control gate electrode on said second gate electrode through an inter-layer gate insulation film; and forming said floating gate electrode of each of said memory transistors by patterning said second and first gate electrodes in self-alignment with said control gate electrode.
Claim 6
Independent Claim
226 words
A method of manufacturing a semiconductor device having a memory cell array in which non-volatile memory transistors each including a floating gate electrode and a control gate electrode coupled in capacity thereto are formed in array, said method comprising the steps of: sequentially depositing a first gate electrode and a mask layer on a semiconductor substrate through a gate insulation film; forming a trench in an element isolation region by etching said first gate electrode, said gate insulation film and said semiconductor substrate in sequence by anisotropic etching; filling an element isolation insulation film in said trench substantially flush with said mask layer, with said mask layer remaining left; removing at least a part of said mask layer in a layer thicknesswise direction thereof, and thereafter recessing an upper edge corner of said element isolation insulation film by isotropic etching; a step of removing said mask layer, and thereafter depositing a second gate electrode composing said floating gate electrode together with said first gate electrode; forming a slit for isolating said second gate electrode in said element isolation insulation film; a step of providing said control gate electrode on said second gate electrode through an inter-layer gate insulation film; and forming said floating gate electrode of each of said memory transistors by patterning said second and first gate electrodes in self-alignment with said control gate electrode.
References Cited (Backward Citations)
US6281103B1
Cited
JPH07297300A
Cited
US6069055A
Cited
US5858830A
Cited
US6034393A
Cited
US6130129A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-01 | 2005-12-31 | 2006-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-01 | 2009-12-31 | 2010-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-01 | 2013-12-31 | 2014-07-02 | $7700.00 | Window Closed / Lapsed |