US6380760B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit for handling buffer contention and method thereof
Assignee: VLSI Technology LLC
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Filing: 2000-08-11
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Granted: 2002-04-30
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Expires: 2020-08-11
Abstract
Abstract In one embodiment, an integrated circuit ( 10, 110 ) has a contention detection circuit ( 12, 112 ) coupled to a tri-stateable output buffer ( 18, 118 ). The contention detection circuit ( 12, 112 ) provides a contention tri-state control signal ( 34, 134 ) to the tri-stateable output buffer ( 18, 118 ) in order to place it in a tri-stated condition when an external device ( 31, 131 ), such as a computer, supplies power to an input/output pad ( 22, 122 ) on the integrated circuit ( 10, 110 ). Thus, external and/or internal buffer contention is avoided when an external device ( 31, 131 ), such as a computer, supplies power to an input/output pad ( 22, 122 ) on the integrated circuit ( 10, 110 ).
Inventors
- 👤 Bernard J. Pappert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; Y; Y10; Y10T; Y10T83/00; Y10T83/202; Y10T83/2033; Y10T83/2037
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
122 words
An integrated circuit having a powered-off state and a powered-on state, the integrated circuit powered in the powered-on state by a first power supply voltage, the integrated circuit comprising: a first terminal to receive the first power supply voltage; a second terminal to couple to an external device, the external device providing a second power supply voltage; a tri-stateable output buffer coupled to the first and second terminals; and a contention detection circuit coupled to the tri-stateable output buffer, the contention detection circuit to place the tri-stateable output buffer in a tri-stated condition when the second power supply voltage is present at the second terminal and the first power supply voltage is absent from the first terminal, thereby minimizing undesired buffer contention.
Claim 2
Dependent Claim
122 words
An integrated circuit having a powered-off state and a powered-on state, the integrated circuit powered in the powered-on state by a first power supply voltage, the integrated circuit comprising: a first terminal to receive the first power supply voltage; a second terminal to couple to an external device, the external device providing a second power supply voltage; a tri-stateable output buffer coupled to the first and second terminals; and a contention detection circuit coupled to the tri-stateable output buffer, the contention detection circuit to place the tri-stateable output buffer in a tri-stated condition when the second power supply voltage is present at the second terminal and the first power supply voltage is absent from the first terminal, thereby minimizing undesired buffer contention.
Claim 3
Dependent Claim
47 words
An integrated circuit according to claim 1 wherein the second power supply voltage powers the tri-stateable output buffer and the contention detection circuit when the second power supply voltage is present at the second terminal and the first power supply voltage is absent from the first terminal.
Claim 4
Dependent Claim
35 words
An integrated circuit according to claim 1 wherein the contention detection circuit does not place the tri-stateable output buffer in a tri-stated condition when the first power supply voltage is present at the first terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-29 | 2005-10-29 | 2006-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-29 | 2009-10-29 | 2010-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-29 | 2013-10-29 | 2014-04-30 | $7700.00 | Window Closed / Lapsed |