Abstract A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded. The configuration processor determines which IOBs received reflected test pulses, and which have not. The configuration processor adjusts the slew rate in the IOBs receiving a reflected test pulse, and repeats the test until there are no reflected test pulses.
A programmable device comprising: a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer; an adjustable slew rate control circuit coupled to each output buffer, wherein each adjustable slew rate control circuit is programmable to control the slew rate of an associated output buffer; an asynchronous latch coupled to each input buffer; and a variable pulse generator coupled to each output buffer.
Claim 2
Dependent Claim
67 words
A programmable device comprising: a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer; an adjustable slew rate control circuit coupled to each output buffer, wherein each adjustable slew rate control circuit is programmable to control the slew rate of an associated output buffer; an asynchronous latch coupled to each input buffer; and a variable pulse generator coupled to each output buffer.
Claim 3
Dependent Claim
15 words
The programmable device of claim 1, wherein the variable pulse generator comprises a delay line.
Claim 4
Dependent Claim
14 words
The programmable device of claim 1, wherein each output buffer is a tri-state buffer.
Claim 5
Dependent Claim
27 words
The programmable device of claim 1, further comprising a plurality of switches, wherein each switch is located between the variable pulse generator to an associated output buffer.
Claim 6
Dependent Claim
45 words
The programmable device of claim 1, wherein each slew rate control circuit is coupled to a JTAG register, such that information identifying the current slew rate of the slew rate control circuit can be transferred from the slew rate control circuit to the JTAG register.