MOS output buffer with overvoltage protection circuitry

Claim 2

An output circuit comprising: an output terminal; a power-supply node for receiving either a first power-supply potential or a second power-supply potential; a first MOS transistor having a source, a drain, a gate connected to receive a control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said power-supply node and said output terminal; a second MOS transistor of the same channel type as said first MOS transistor, having a source, a drain, a gate and a back gate, and a source-drain path connected between the back gate and gate of said first MOS transistor, and controlled to be off when the first power-supply potential is applied to said power-supply node and to be on when the second power-supply potential is applied to said power-supply node; and a third MOS transistor of the same channel type as said first MOS transistor, having a source-drain path connected between said output terminal and the end of the source-drain path of said second MOS transistor which is connected to said back gate of said first MOS transistor.

Claim 3

The output circuit according to claim 1, wherein the back gate of said second MOS transistor is connected to the back gate of said first MOS transistor, and the gate of said second MOS transistor is connected to said power-supply node.

Claim 4

An output circuit comprising: an output terminal; a first power-supply node for receiving either a first power-supply potential or a second power-supply potential; a second power-supply node for receiving the second power-supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate connected to receive a control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said first power-supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between the back gate and the gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said second power-supply node and a second end of the source-drain path of said third MOS transistor; first control-signal generating circuit for generating the control signal from a first signal and for supplying the control signal to the gate of said first MOS transistor, said first control-signal generating circuit comprising: a fifth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor; a sixth MOS transistor of the first channel type, having a source, a drain, a gate for receiving a first signal, and a source-drain path connected in series to the source-drain path of said fifth MOS transistor; and a seventh MOS transistor of the second channel type, having a source, a drain, a gate for receiving the first signal, and a source-drain path connected between the gate of said first MOS transistor and said second power-supply node; and a second control-signal generating circuit for receiving power-supply voltages which are voltages at said first and second power-supply nodes, and generating the first signal to be supplied to the gates of said sixth and seventh MOS transistors.

Claim 5

An output circuit comprising: an output terminal; a first power-supply node for receiving either a first power-supply potential or a second power-supply potential; a second power-supply node for receiving the second power-supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate connected to receive a control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said first power-supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between the back gate and the gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said second power-supply node and a second end of the source-drain path of said third MOS transistor; first control-signal generating circuit for generating the control signal from a first signal and for supplying the control signal to the gate of said first MOS transistor, said first control-signal generating circuit comprising: a fifth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor; a sixth MOS transistor of the first channel type, having a source, a drain, a gate for receiving a first signal, and a source-drain path connected in series to the source-drain path of said fifth MOS transistor; and a seventh MOS transistor of the second channel type, having a source, a drain, a gate for receiving the first signal, and a source-drain path connected between the gate of said first MOS transistor and said second power-supply node; and a second control-signal generating circuit for receiving power-supply voltages which are voltages at said first and second power-supply nodes, and generating the first signal to be supplied to the gates of said sixth and seventh MOS transistors.

Claim 6

The output circuit according to claim 3, wherein the source-drain path of said fifth MOS transistor is connected at a first end to said first power-supply node, the source-drain path of said second MOS transistor is connected at a first end to the back gate of said first MOS transistor and at a second end to a second end of the source-drain path of said fifth MOS transistor.

Claim 7

The output circuit according to claim 3, wherein the source-drain path of said second MOS transistor is connected at the first end to the back gate of said first MOS transistor and at the second end to the gate of said first MOS transistor.

Claim 8

The output circuit according to claim 3, wherein said first control-signal generating circuit comprises an eighth MOS transistor of the second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between the gate of said first MOS transistor and said second power-supply node and in series to the source-drain path of said seventh MOS transistor.

Claim 9

The output circuit according to claim 3, further comprising an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between the back gate of said first MOS transistor and said output terminal.

Claim 10

The output circuit according to claim 3, further comprising an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the back gate of said first MOS transistor.

Claim 11

The output circuit according to claim 3, further comprising: an eighth MOS transistor of the second channel type, having a source, a drain, a gate, and a source-drain path connected between said output terminal and said second power-supply node; and a third control-signal generating circuit for receiving voltage at said first power-supply node and voltage at said second power-supply node and for generating a control signal to be supplied to the gate of said eighth MOS transistor.

Claim 12

The output circuit according to claim 3, further comprising: an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to the gate of said first MOS transistor, and a source-drain path connected between said first power-supply node and the back gate of said first MOS transistor; and a ninth MOS transistor of the first channel type, having a source, a drain, a gate connected to said output terminal and a source-drain path connected between said first power-supply node and the back gate of said first MOS transistor.

Claim 13

An output circuit comprising: an output terminal; a first power-supply node for receiving either a first power-supply potential or a second power-supply potential; a second power-supply node for receiving the second power-supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate connected to receive a control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said first power-supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate, a source-drain path connected between the back gate and gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said second power-supply node and a second end of the source-drain path of said third MOS transistor; a first control-signal generating circuit for generating the control signal from a plurality of signals and for supplying the control signal to the gate of said first MOS transistor, said first control-signal generating circuit comprising: a fifth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor; a plurality of sixth MOS transistors of the first channel type, each having a source, a drain, a gate for receiving one of said plurality of signals, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor and in series to the source-drain path of said fifth MOS transistor; and a plurality of seventh MOS transistors of the second channel type, each having a source, a drain, a gate for receiving one of said plurality of signals, and a source-drain path connected in series between the gate of said first MOS transistor and said second power-supply node; and a second control-signal generating circuit for receiving power-supply voltages which are voltages at said first and second power-supply nodes, and generating any one of said plurality signals to be supplied to the gates of said sixth and seventh MOS transistors.

Claim 14

An output circuit comprising: an output terminal; a first power-supply node for receiving either a first power-supply potential or a second power-supply potential; a second power-supply node for receiving the second power-supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate connected to receive a control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said first power-supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate, a source-drain path connected between the back gate and gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said second power-supply node and a second end of the source-drain path of said third MOS transistor; a first control-signal generating circuit for generating the control signal from a plurality of signals and for supplying the control signal to the gate of said first MOS transistor, said first control-signal generating circuit comprising: a fifth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor; a plurality of sixth MOS transistors of the first channel type, each having a source, a drain, a gate for receiving one of said plurality of signals, and a source-drain path connected between said first power-supply node and the gate of said first MOS transistor and in series to the source-drain path of said fifth MOS transistor; and a plurality of seventh MOS transistors of the second channel type, each having a source, a drain, a gate for receiving one of said plurality of signals, and a source-drain path connected in series between the gate of said first MOS transistor and said second power-supply node; and a second control-signal generating circuit for receiving power-supply voltages which are voltages at said first and second power-supply nodes, and generating any one of said plurality signals to be supplied to the gates of said sixth and seventh MOS transistors.

Claim 15

The output circuit according to claim 11, wherein the source-drain path of said second MOS transistor is connected at a first end to the back gate of said first MOS transistor and at a second end to the gate of said first MOS transistor.

Claim 16

The output circuit according to claim 11, wherein the source-drain path of said second MOS transistor is connected at a first end to the back gate of said first MOS transistor and at a second end to a first end of the source-drain path of said fifth MOS transistor, which is closer to the gate of said first MOS transistor than a second end.

Claim 17

The output circuit according to claim 11, further comprising an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said output terminal and the back gate of said first MOS transistor.

Claim 18

The output circuit according to claim 11, further comprising an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of said third and fourth MOS transistors, and a source-drain path connected between said first power-supply node and the back gate of said first MOS transistor.

Claim 19

The output circuit according to claim 11, further comprising: an eighth MOS transistor of the second channel type, having a source, a drain, a gate, and a source-drain path connected between said output terminal and said second power-supply node; and a third control-signal generating circuit for receiving power-supply voltages which are voltages at said first power-supply node and said second power-supply node, and for generating a control signal in response to said plurality of signals and supplying the control signal to the gate of said eighth MOS transistor.

Claim 20

The output circuit according to claim 11, further comprising: an eighth MOS transistor of the first channel type, having a source, a drain, a gate connected to the gate of said first MOS transistor, and a source-drain path connected between said first power-supply node and the back gate of said first MOS transistor; and a ninth MOS transistor of the first channel type, having a source, a drain, a gate connected to said output terminal, and a source-drain path connected between the first power-supply node and the back gate of said first MOS transistor.

Claim 21

An output circuit comprising: an output terminal; a first power supply node for receiving either a first power supply potential or a second power supply potential; a second power supply node for receiving the second power supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate coupled to receive a first control signal, a back gate isolated from the source in terms of potential, and a source-drain path coupled between said first power supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled between the back gate and the gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled between said second power supply node and a second end of the source-drain path of said third MOS transistor; and a first control signal generating circuit coupled to said third and fourth MOS transistors for generating the first control signal and supplying the first control signal to the gate of said first MOS transistor.

Claim 22

An output circuit comprising: an output terminal; a first power supply node for receiving either a first power supply potential or a second power supply potential; a second power supply node for receiving the second power supply potential; a first MOS transistor of a first channel type, having a source, a drain, a gate coupled to receive a first control signal, a back gate isolated from the source in terms of potential, and a source-drain path coupled between said first power supply node and said output terminal; a second MOS transistor of the first channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled between the back gate and the gate of said first MOS transistor; a third MOS transistor of the first channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled at a first end to said output terminal; a fourth MOS transistor of a second channel type, having a source, a drain, a gate coupled to said first power supply node, and a source-drain path coupled between said second power supply node and a second end of the source-drain path of said third MOS transistor; and a first control signal generating circuit coupled to said third and fourth MOS transistors for generating the first control signal and supplying the first control signal to the gate of said first MOS transistor.

Claim 23

The output circuit according to claim 18, further comprising: a second control signal generating circuit for generating second control signals from power supply voltages and supplying the second control signals to said first control signal generating circuit.