Patent US6373334B1 successfully refreshed from Google Patents.
US6373334B1
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Real time correction of a digital PWM amplifier
Assignee: Cirrus Logic Inc
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Filing: 2000-06-12
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Granted: 2002-04-16
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Expires: 2020-06-12
Abstract
Abstract Distortion and noise in high power digital PWM amplifiers is reduced by measuring the difference between the desired output signal and the actual output signal on a pulse by pulse basis. This analog error is converted into a digital signal with an analog to digital converter (ADC). The digital error signal is then used to correct the feedback of the delta sigma modulator in real time. Preferably, more than one moment of the modulator signal is corrected via the feedback. Preferably, the predictable error of the circuitry which is known a priori is also corrected by correcting the delta sigma modulator feedback. A specialized ADC allows the loop delay to be low, without compromising accuracy.
Inventors
- 👤 John Laurence Melanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:11
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H03F3/2175; H03M; H03M1/00; H03M1/12; H03M1/1235; H03M3/00; H03M3/30; H03M3/322; H03M3/358; H03M3/38; H03M3/386; H03M3/388; H03F2200/00; H03F2200/453; H03M3/50; H03M3/502; H03M3/506
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
118 words
A digital PWM amplifier of the type having a multilevel delta sigma modulator of at least second order, having at least two state variables feeding a quantizer which provides feedback to the state variables and an output signal driving a PWM, the PWM feeding Class D output stage drivers, wherein the improvement comprises: means for comparing the output of the PWM with the output of the drivers, and generating an analog error signal based upon the comparison; an analog to digital converter (ADC) for converting the analog error signal into a digital error signal; and real time correction means for correcting the feedback of the delta sigma modulator on an ongoing basis based upon the digital error signal.
Claim 2
Dependent Claim
118 words
A digital PWM amplifier of the type having a multilevel delta sigma modulator of at least second order, having at least two state variables feeding a quantizer which provides feedback to the state variables and an output signal driving a PWM, the PWM feeding Class D output stage drivers, wherein the improvement comprises: means for comparing the output of the PWM with the output of the drivers, and generating an analog error signal based upon the comparison; an analog to digital converter (ADC) for converting the analog error signal into a digital error signal; and real time correction means for correcting the feedback of the delta sigma modulator on an ongoing basis based upon the digital error signal.
Claim 3
Dependent Claim
55 words
The apparatus of claim 1 , wherein the ADC generates a first and a second digital error signal corresponding to a first and a second integral of the analog error signal, and wherein feedbacks to different state variables of the delta sigma modulator are corrected differently according to the first and second digital error signals.
Claim 4
Dependent Claim
25 words
The apparatus of claim 2 , further including a priori correction means for applying different correction factors based upon predictable errors to the state variables.
Claim 5
Dependent Claim
94 words
The apparatus of claim 2 , wherein the ADC comprises: at least two integrators in series; feedback logic for generating feedback signals based upon the digital error signals; the first integrator fed by the analog error signal and a first feedback signal from the feedback logic; the second integrator fed by the output of the first integrator and a second feedback signal from the feedback logic; and two flash ADCs each having an output of one the integrators as its analog input and providing one of the digital error signals as its digital output.
Claim 6
Dependent Claim
59 words
The apparatus of claim 4 , wherein the feedback logic comprises: means for generating a first feedback signal based on the negative of the first digital error signal; and means for generating a second feedback signal based on the negative of the second digital error signal combined with a fraction of the negative of the first digital error signal.
Claim 7
Dependent Claim
18 words
The apparatus of claim 4 , further including means for measuring a gain of each of the integrators.
Claim 8
Dependent Claim
18 words
The apparatus of claim 6 , further including means for adjusting a gain of each of the integrators.
Claim 9
Dependent Claim
29 words
The apparatus of claim 2 , further including means for measuring and compensating for a relative delay between the output of the PWM and the output of the drivers.
Claim 10
Dependent Claim
24 words
The apparatus of claim 8 , wherein the measuring and compensating means comprises adjustable delay means connected between the PWM and the comparing means.
Claim 11
Dependent Claim
35 words
The apparatus of claim 8 , wherein the measuring and compensating means comprises fixed delay means connected between the PWM and the comparing means and adjustable delay means connected between the PWM and the drivers.
Claim 12
Independent Claim
114 words
A method for improving the performance of a digital PWM amplifier of the type having a multilevel delta sigma modulator of at least second order, having at least two state variables feeding a quantizer which provides feedback to the state variables and an output signal driving a PWM, the PWM feeding Class D output stage drivers, wherein the method comprises the steps of: comparing the output of the PWM with the output of the drivers, and generating an analog error signal based upon the comparison; converting the analog error signal into a digital error signal; and correcting the feedback of the delta sigma modulator on an ongoing basis based upon the digital error signal.
Claim 13
Independent Claim
114 words
A method for improving the performance of a digital PWM amplifier of the type having a multilevel delta sigma modulator of at least second order, having at least two state variables feeding a quantizer which provides feedback to the state variables and an output signal driving a PWM, the PWM feeding Class D output stage drivers, wherein the method comprises the steps of: comparing the output of the PWM with the output of the drivers, and generating an analog error signal based upon the comparison; converting the analog error signal into a digital error signal; and correcting the feedback of the delta sigma modulator on an ongoing basis based upon the digital error signal.
Claim 14
Dependent Claim
55 words
The method of claim 11 , further including the steps of: generating a first and a second digital error signal corresponding to a first and a second integral of the analog error signal, and correcting feedbacks to different state variables of the delta sigma modulator differently according to the first and second digital error signals.
Claim 15
Dependent Claim
144 words
The method of claim 12 , further including a method for deriving correction functions for application by the correcting feedbacks step comprising the steps of: determining a system equivalent to the delta sigma modulator, the equivalent system operating at a higher clock rate, the higher clock rate being a multiple of the operating clock rate, wherein the output of the system is substantially linear at the higher clock rate; modeling the response to system operation at the higher clock rate; modelling the correction to be applied to each integrator feedback path at the higher clock rate to correct modelled distortion; computing the correction functions to be applied within the modulator at the operating clock rate such that the modulator operating at the operating clock rate substantially matches the operation of the system operating at the higher clock rate in response to the same outputs.
Claim 16
Dependent Claim
34 words
The method of claim 13 , wherein the step of computing the correction includes the steps of determining the roots of the state transition matrix and computing the correction functions based on the roots.
Claim 17
Dependent Claim
31 words
The method of claim 12 , further including a priori correction step of applying different correction factors to feedbacks to different state variables based upon predictable errors to the state variables.
Claim 18
Dependent Claim
69 words
The apparatus of claim 12 , wherein the step of converting the analog error signal into digital error signals comprises: (a) generating feedback signals based upon the digital error signals; (b) finding the integral of the analog error signal and a first feedback signal; (c) finding the integral of the integral generated in step (b) and a second feedback signal; and (d) converting the integrals into digital error signals.
Claim 19
Dependent Claim
56 words
The method of claim 16 , wherein the feedback generating step comprises: generating a first feedback signal based on the negative of the first digital error signal; and generating a second feedback signal based on the negative of the second digital error signal combined with a fraction of the negative of the first digital error signal.
Claim 20
Dependent Claim
21 words
The method of claim 16 , further including the step of measuring a gain of each of the integral generating steps.
Claim 21
Dependent Claim
20 words
The method of claim 18 , further including the step of adjusting gain of each of the integral generating steps.
Claim 22
Dependent Claim
30 words
The method of claim 11 , further including the steps of measuring and compensating for a relative delay between the output of the PWM and the output of the drivers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-04-15 | 2005-10-15 | 2006-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-15 | 2009-10-15 | 2010-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-15 | 2013-10-15 | 2014-04-16 | $7700.00 | Window Closed / Lapsed |