Delta-sigma pulse width modulator control circuit

Claim 2

A control circuit for controlling power delivered to a load with reduced spurious electromagnetic energy generation, comprising: a delta sigma modulator accepting a first signal and generating a second signal representing said first signal with a plurality of digital pulses; and a pulse width modulator coupled to said delta sigma modulator, accumulating said second signal over a first time period, and generating a third signal coupled to the load and having a first magnitude value, said first magnitude value lasting for a second time period related to said second signal, said pulse width modulator further comprises: a pulse counter that multiplies each pulse of said plurality of digital pulses with a weight, said weight determined by position of each pulse relative to commencement of said first time period, thereby creating a plurality of weighted pulses, and said pulse counter accumulates said weighted pulses over said first time period, a low pass filter, coupled to said pulse counter, to generate a filtered bit stream, and a waveform generator, coupled to said low pass filter to generate, from said filtered bit stream, said third signal including a third time period greater than and encompassing said second time period.

Claim 3

The control circuit in accordance with claim 1 wherein, said delta sigma modulator further comprises a first order delta sigma modulator.

Claim 4

The control circuit in accordance with claim 1 wherein, said delta sigma modulator further comprises a second order delta sigma modulator.

Claim 5

The control circuit in accordance with claim 1 wherein, said delta sigma modulator further comprises a three stage cascaded delta sigma modulator.

Claim 6

A control circuit for controlling power delivered to a load with reduced spurious electromagnetic energy generation, comprising: a delta sigma modulator accepting a first signal and generating a second signal representing said first signal with a plurality of digital pulses thereby creating second signal pulses; and a pulse width modulator coupled to said delta sigma modulator, accumulating said second signal over a first time period, and generating a third signal coupled to the load and having a first magnitude value, said first magnitude value lasting for a second time period related to said second signal, said pulse width modulator further comprises: a pulse counter that multiplies each pulse of said plurality of digital pulses with a weight, said weight determined by position of each pulse relative to commencement of said first time period, thereby creating a plurality of weighted pulses, and said pulse counter accumulates said weighted pulses over said first time period, a low pass filter, coupled to said pulse counter, to generate a filtered bit stream, a waveform generator, coupled to said low pass filter to generate, from said filtered bit stream, said third signal including a third time period greater than and encompassing said second time period, a pulse width indicator to indicate when an accumulation of said second signal pulses create lasting for greater than 50% of said third time period, and a pulse protocol inverter coupled to said pulse width indicator to transform said third signal from an active high first magnitude value protocol to an active low first magnitude value protocol.

Claim 7

A control circuit for controlling power delivered to a load with reduced spurious electromagnetic energy generation, comprising: a delta sigma modulator accepting a first signal and generating a second signal representing said first signal with a plurality of digital pulses thereby creating second signal pulses; and a pulse width modulator coupled to said delta sigma modulator, accumulating said second signal over a first time period, and generating a third signal coupled to the load and having a first magnitude value, said first magnitude value lasting for a second time period related to said second signal, said pulse width modulator further comprises: a pulse counter that multiplies each pulse of said plurality of digital pulses with a weight, said weight determined by position of each pulse relative to commencement of said first time period, thereby creating a plurality of weighted pulses, and said pulse counter accumulates said weighted pulses over said first time period, a low pass filter, coupled to said pulse counter, to generate a filtered bit stream, a waveform generator, coupled to said low pass filter to generate, from said filtered bit stream, said third signal including a third time period greater than and encompassing said second time period, a pulse width indicator to indicate when an accumulation of said second signal pulses create lasting for greater than 50% of said third time period, and a pulse protocol inverter coupled to said pulse width indicator to transform said third signal from an active high first magnitude value protocol to an active low first magnitude value protocol.

Claim 8

A control circuit in accordance with claim 5 further comprising: a delay generator coupled to said waveform generator and generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and a delay generator disable coupled to said delay generator and said pulse protocol inverter for forcing said time delay to be zero time when said first time period has said active low first magnitude value protocol and is immediately followed by a following first period having said active high first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.

Claim 9

A control circuit in accordance with claim 5 further comprising: a delay generator coupled to said waveform generator and generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and a delay generator disable coupled to said delay generator and said pulse protocol inverter for forcing said time delay to be zero time when said first time period has said active high first magnitude value protocol and is immediately followed by a following first period having said active low first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.

Claim 10

A control circuit in accordance with claim 5 further comprising: a delay generator coupled to said waveform generator and generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and a delay generator disable coupled to said delay generator and said pulse protocol inverter for forcing said time delay to be zero time when said first time period has said active high first magnitude value protocol and is immediately followed by a following first period having said active low first magnitude value protocol and when said first time period has said active low first magnitude value protocol and is immediately followed by said following first period having said active high first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.

Claim 13

A method in accordance with the method of claim 9 further comprising the step of generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay.

Claim 14

A method in accordance with the method of claim 10 further comprising the steps of: generating a fourth signal representing said third time period dividing by a factor of two, said forth signal to generate a halved fourth signal; and outputting a two state signal representing with a first state that said accumulated second signal is greater than said halved fourth signal, thereby indicating that said second time period exceeds 50% of said third time period, and representing with a second state that said accumulated second signal is less than said halved fourth signal, thereby indicating that said second time period does not exceed 50% of said third time period.

Claim 15

A method in accordance with the method of claim 11 further comprising the steps of: subtracting said accumulated second signal from said fourth signal representing said third time period thereby generating a difference signal; and receiving an indication when said second time period exceeds 50% of said third time period; outputting said accumulated second signal as said difference signal upon said exceeding of 50%; and outputting said difference signal as said accumulated second signal upon said exceeding of 50%.

Claim 18

A method in accordance with the method of claim 13 further comprising the steps of: generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and forcing said time delay to be zero time when said first time period has said active low first magnitude value protocol and is immediately followed by a following first period having said active high first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.

Claim 19

A method in accordance with the method of claim 13 further comprising the steps of: generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and forcing said time delay to be zero time when said first time period has said active high first magnitude value protocol and is immediately followed by a following first period having said active low first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.

Claim 20

A method in accordance with the method of claim 13 further comprising the steps of: generating a time delay to offset a commencement of said second time period from a commencement of said third time period by a time equal to said time delay; and forcing said time delay to be zero time when said first time period has said active low first magnitude value protocol and is immediately followed by a following first period having said active high first magnitude value protocol and when said first time period has said active high first magnitude value protocol and is immediately followed by said following first period having said active low first magnitude value protocol, thereby reducing the number of transitions from said first magnitude value to a second magnitude value during said following first period.