Patent US6356122B2 successfully refreshed from Google Patents.
US6356122B2
Expired / Lapsed
US
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Clock synthesizer with programmable input-output phase relationship
Assignee: PLL Technologies Inc
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Filing: 1999-08-04
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Granted: 2002-03-12
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Expires: 2019-08-04
Abstract
Abstract A circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.
Inventors
- 👤 Piyush Sevalia
- 👤 J. Ken Fox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:26
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/16; H03L7/18; H03L7/183; H03L7/22; H03L7/23; H03L2207/00; H03L2207/10
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
63 words
A clock circuit, comprising: an oscillator, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output; a reference path providing said reference signal from a reference clock input; and a feedback path providing said feedback signal from the oscillator output; wherein each of the reference path and the feedback path comprises a programmable delay circuit.
Claim 2
Dependent Claim
63 words
A clock circuit, comprising: an oscillator, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output; a reference path providing said reference signal from a reference clock input; and a feedback path providing said feedback signal from the oscillator output; wherein each of the reference path and the feedback path comprises a programmable delay circuit.
Claim 3
Dependent Claim
25 words
The circuit according to claim 1 , further comprising a logic circuit configured to select a characteristic or predetermined delay for the programmable delay circuit.
Claim 4
Dependent Claim
21 words
The circuit according to claim 2 , further comprising a divider configured to provide a divided output from the oscillator output.
Claim 5
Dependent Claim
33 words
The circuit according to claim 1 , further comprising: a second oscillator configured to provide a second output; and a multiplexer configured to select one of the oscillator outputs as a clock output.
Claim 6
Dependent Claim
37 words
The circuit according to claim 3 , wherein the logic circuit is further configured to select an input for the feedback path from at least two of the oscillator output, the divided output, and the clock output.
Claim 7
Dependent Claim
45 words
The circuit according to claim 5 , wherein the reference path further comprises a reference counter receiving the reference clock input providing said reference signal therefrom, and the feedback path further comprises a feedback counter receiving the feedback path input providing said feedback signal therefrom.
Claim 8
Dependent Claim
64 words
A circuit comprising: means for generating an output in response to (i) a reference input receiving a reference signal and (ii) a feedback input receiving a feedback signal; means for generating said reference signal from a reference clock input; and means for generating said feedback signal from the output, wherein each of the reference path and the feedback path comprises a programmable delay circuit.
Claim 9
Dependent Claim
64 words
A circuit comprising: means for generating an output in response to (i) a reference input receiving a reference signal and (ii) a feedback input receiving a feedback signal; means for generating said reference signal from a reference clock input; and means for generating said feedback signal from the output, wherein each of the reference path and the feedback path comprises a programmable delay circuit.
Claim 10
Independent Claim
48 words
A method of controlling a clock output, comprising the steps of: generating the clock output in response to a reference input and a feedback input; and delaying each of the reference input and the feedback input by a programmable amount of time to thereby control the clock output.
Claim 11
Independent Claim
48 words
A method of controlling a clock output, comprising the steps of: generating the clock output in response to a reference input and a feedback input; and delaying each of the reference input and the feedback input by a programmable amount of time to thereby control the clock output.
Claim 12
Dependent Claim
24 words
The method according to claim 8 , further comprising the step of programming one or more programmable elements controlling the programmable amount of time.
Claim 13
Dependent Claim
16 words
The circuit according to claim 1 , wherein said clock circuit comprises a phase locked loop.
Claim 14
Dependent Claim
15 words
The circuit according to claim 1 , wherein said clock circuit comprises a delayed-lock loop.
Claim 15
Dependent Claim
14 words
The circuit according to claim 1 , wherein said oscillator comprises a ring oscillator.
Claim 16
Dependent Claim
17 words
The circuit according to claim 4 , wherein said second oscillator further comprises a phase locked loop.
Claim 17
Dependent Claim
18 words
The method according to claim 8 , wherein said clock output is generated by a phase locked loop.
Claim 18
Dependent Claim
17 words
The method according to claim 8 , wherein said clock output is generated by a delayed-lock loop.
Claim 19
Dependent Claim
17 words
The method according to claim 8 , wherein said clock output is generated by a ring oscillator.
Claim 20
Dependent Claim
23 words
The method according to claim 8 , wherein said method further comprises the step of: producing a divided output from an oscillator output.
Claim 21
Dependent Claim
31 words
The method according to claim 17 , wherein said method further comprises the steps of: generating a second oscillator output; and selecting one of the oscillator outputs as said clock output.
Claim 22
Dependent Claim
57 words
The method according to claim 18 , wherein said wherein said method further comprises the steps of: selecting a characteristic or predetermined delay for the programmable amount of time; and selecting an input for a feedback path from at least two of (i) one of the oscillator outputs, (ii) the divided output, and (iii) the clock output.
Claim 23
Dependent Claim
43 words
The method according to claim 19 , wherein said method further comprises the steps of: providing a reference signal generated by a reference counter receiving the reference input; and providing a feedback signal generated by a feedback counter receiving the feedback path input.
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