US6353841B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reconfigurable processor devices
Assignee: Panasonic Holdings Corp
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Filing: 1998-12-11
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Granted: 2002-03-05
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Expires: 2018-12-11
Abstract
Abstract The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the processing devices comprises an arithmetic logic unit, which is adapted to perform a function on input operands and produce an output. The input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle. Dynamic instructions are enabled by means provided to route the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.
Inventors
- 👤 Alan David Marshall
- 👤 Anthony Stansfield
- 👤 Jean Vuillemin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:31
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F7/53; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/38; G06F9/3885; G06F9/3893; G06F9/3895; G06F9/3897; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17748; H03K19/17752; H03K19/17756; H03K19/1776
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
115 words
A reconfigurable device comprising: a plurality of processing devices; a connection matrix providing an interconnect between the processing devices; and means to define a configuration of the connection matrix; wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle, and wherein the connection matrix is adapted to direct the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.
Claim 2
Dependent Claim
115 words
A reconfigurable device comprising: a plurality of processing devices; a connection matrix providing an interconnect between the processing devices; and means to define a configuration of the connection matrix; wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle, and wherein the connection matrix is adapted to direct the output of a first one of the processing devices to a second one of the processing devices to determine the function performed by the second one of the processing devices.
Claim 3
Dependent Claim
34 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices contains no addressable input register, whereby input operands are received directly from the interconnect by the arithmetic logic unit.
Claim 4
Dependent Claim
57 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices has a first plurality of configuration bits which can be determined by the output of another one of the processing devices and a second plurality of configuration bits which cannot be determined by the output of another one of the processing devices.
Claim 5
Dependent Claim
69 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices has a first operand input, a second operand input, a function result output, a carry input and a carry output, wherein the first operand input, the second operand input and the function result output are n-bit, where n is an integer greater than 1, and the carry input and the carry output are 1-bit.
Claim 6
Dependent Claim
15 words
A reconfigurable device as claimed in claim 4 , wherein n is equal to 4.
Claim 7
Dependent Claim
34 words
A reconfigurable device as claimed in claim 4 , wherein each of the processing devices is adapted to receive, for determination of its function, an n-bit instruction input from another of the processing devices.
Claim 8
Dependent Claim
37 words
A reconfigurable device as claimed in claim 4 , wherein means are provided to allow the carry input to one of the processing devices to change the function of the arithmetic logic unit of that processing device.
Claim 9
Dependent Claim
29 words
A reconfigurable device as claimed in claim 7 , wherein said means allows the carry input to change the function of the arithmetic logic unit to its logical complement.
Claim 10
Dependent Claim
31 words
A reconfigurable device as claimed in claims 4 , wherein means are provided for each of the processing devices to enable the carry input to be held at a constant value.
Claim 11
Dependent Claim
51 words
A reconfigurable device as claimed in claim 4 , wherein a first one of the processing devices is usable to multiplex between two values of an instruction input to a second one of the processing devices according to the value of the carry input of the first of the processing devices.
Claim 12
Dependent Claim
41 words
A reconfigurable device as claimed in claim 10 , wherein the carry input of the first of the processing devices can be propagated through the first of the processing devices to the carry input of the second of the processing devices.
Claim 13
Dependent Claim
24 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices comprises a latchable output register for the function output.
Claim 14
Dependent Claim
53 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices comprises a dynamic enable gate to determine whether instructions to determine the function of the arithmetic logic unit are to be accepted dynamically from the interconnect or are to be provided from configuration memory in the processing device.
Claim 15
Dependent Claim
73 words
A reconfigurable device as claimed in claim 1 , wherein each of the processing devices comprises a dynamic instruction mask whereby application of the dynamic instruction mask to an instruction received by the processing device enables the instruction to provide both an instruction input to the arithmetic logic unit for determining the function of the arithmetic logic unit and a peripheral circuitry instruction input for control of peripheral circuitry in the processing device.
Claim 16
Independent Claim
174 words
A method of constructing a central processing unit from a reconfigurable device, the reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices; and means to define a configuration of the connection matrix, the method comprising: allocating one or more of the processing devices to form an arithmetic logic unit of the central processing unit, wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, and wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle; associating a first memory, as a register file, with the arithmetic logic unit of the central processing unit; and associating a second memory, as a code memory, with the arithmetic logic unit of the central processing unit, to provide instructions for the central processing unit, wherein instruction inputs for the arithmetic logic unit of the central processing unit are provided from the second memory.
Claim 17
Independent Claim
174 words
A method of constructing a central processing unit from a reconfigurable device, the reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices; and means to define a configuration of the connection matrix, the method comprising: allocating one or more of the processing devices to form an arithmetic logic unit of the central processing unit, wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, and wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle; associating a first memory, as a register file, with the arithmetic logic unit of the central processing unit; and associating a second memory, as a code memory, with the arithmetic logic unit of the central processing unit, to provide instructions for the central processing unit, wherein instruction inputs for the arithmetic logic unit of the central processing unit are provided from the second memory.
Claim 18
Dependent Claim
48 words
A method as claimed in claim 15 , wherein either or both of the first memory and the second memory are provided by reconfiguration of one or more parts of the reconfigurable device into memory available for use by the central processing unit configured onto the reconfigurable device.
Claim 19
Dependent Claim
31 words
A method as claimed in claim 16 , wherein the one or more parts of the reconfigurable device comprise parts of the means to define the configuration of the connection matrix.
Claim 20
Dependent Claim
33 words
A method as claimed in claim 15 , wherein the central processing unit has multiple arithmetic logic units, and wherein instructions for the multiple arithmetic logic units are provided from the second memory.
Claim 21
Dependent Claim
62 words
A method as claimed in claim 15 , wherein instruction decoder circuitry is provided between the second memory and both the first memory and the arithmetic logic unit of the central processing unit, such that instructions may be stored in compressed form in the second memory and may be decoded by the instruction decoder circuitry before execution in the central processing unit.
Claim 22
Dependent Claim
46 words
A method as claimed in claim 19 , wherein the central processing unit has multiple arithmetic logic units, wherein instructions for the multiple arithmetic logic units are provided from the second memory, and wherein common instruction decoder circuitry is provided for the multiple arithmetic logic units.
Claim 23
Dependent Claim
19 words
A method as claimed in claim 15 , wherein each of the processing devices contains no addressable input register.
Claim 24
Dependent Claim
56 words
A method as claimed in claim 15 , wherein each of the processing devices has a first plurality of configuration bits which can be determined by the output of another one of the processing devices and a second plurality of configuration bits which cannot be determined by the output of another one of the processing devices.
Claim 25
Dependent Claim
68 words
A method as claimed in claim 15 , wherein each of the processing devices has a first operand input, a second operand input, a function result output, a carry input and a carry output, wherein the first operand input, the second operand input and the function result output are n-bit, where n is an integer greater than 1, and the carry input and the carry output are 1-bit.
Claim 26
Dependent Claim
14 words
A method as claimed in claim 23 , wherein n is equal to 4.
Claim 27
Dependent Claim
33 words
A method as claimed in claim 23 , wherein each of the processing devices is adapted to receive, for determination of its function, an n-bit instruction input from another of the processing devices.
Claim 28
Dependent Claim
36 words
A method as claimed in claim 23 , wherein means are provided to allow the carry input to one of the processing devices to change the function of the arithmetic logic unit of that processing device.
Claim 29
Dependent Claim
28 words
A method as claimed in claim 26 , wherein said means allows the carry input to change the function of the arithmetic logic unit to its logical complement.
Claim 30
Dependent Claim
30 words
A method as claimed in claim 23 , wherein means are provided for each of the processing devices to enable the carry input to be held at a constant value.
Claim 31
Dependent Claim
50 words
A method as claimed in claim 23 , wherein a first one of the processing devices is usable to multiplex between two values of an instruction input to a second one of the processing devices according to the value of the carry input of the first of the processing devices.
Claim 32
Dependent Claim
40 words
A method as claimed in claim 29 , wherein the carry input of the first of the processing devices can be propagated through the first of the processing devices to the carry input of the second of the processing devices.
Claim 33
Dependent Claim
23 words
A method as claimed in claim 15 , wherein each of the processing devices comprises a latchable output register for the function output.
Claim 34
Dependent Claim
52 words
A method as claimed in claim 15 , wherein each of the processing devices comprises a dynamic enable gate to determine whether instructions to determine the function of the arithmetic logic unit are to be accepted dynamically from the interconnect or are to be provided from configuration memory in the processing device.
Claim 35
Dependent Claim
72 words
A method as claimed in claim 15 , wherein each of the processing devices comprises a dynamic instruction mask whereby application of the dynamic instruction mask to an instruction received by the processing device enables the instruction to provide both an instruction input to the arithmetic logic unit for determining the function of the arithmetic logic unit and a peripheral circuitry instruction input for control of peripheral circuitry in the processing device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-04 | 2005-09-03 | 2006-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-04 | 2009-09-03 | 2010-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-04 | 2013-09-03 | 2014-03-05 | $7700.00 | Window Closed / Lapsed |