Instruction set modifier register

Claim 2

In a processor comprising a data bus, a plurality of registers and logic circuits, including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instructions, said processor further comprising: an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction decoding and control circuit being responsive to said instruction set modifier register for activating the same ones of said plurality of control lines when any one of a plurality of different instruction words, each from a different instruction set and representing an instruction which is common to each of said instruction sets, is stored in said instruction register, provided that the state of said instruction set modifier register corresponds to that instruction set containing said any one instruction word.

Claim 3

The processor recited in claim 1 wherein said instruction set modifier register is coupled to said data bus and to one of said control lines.

Claim 4

The processor recited in claim 1 wherein said instruction set modifier register comprises at least one bistable logic means.

Claim 5

In a processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, said instruction sets sharing in common at least one instruction representing an operation to be performed by said processor, said at least one instruction being represented by a different instruction word in each of said instruction sets, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a pluality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instructions, said processor further comprising: an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction decoding and control circuit being responsive to said instruction set modifier register for activating the same ones of said plurality of control lines when any one of said instruction words representing said at least one instruction is stored in said instruction register, provided the state of said instruction set modifier register corresponds to that instruction set containing said any one instruction word.

Claim 6

In a processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, said instruction sets sharing in common at least one instruction representing an operation to be performed by said processor, said at least one instruction being represented by a different instruction word in each of said instruction sets, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a pluality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instructions, said processor further comprising: an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction decoding and control circuit being responsive to said instruction set modifier register for activating the same ones of said plurality of control lines when any one of said instruction words representing said at least one instruction is stored in said instruction register, provided the state of said instruction set modifier register corresponds to that instruction set containing said any one instruction word.

Claim 7

The processor recited in claim 4 wherein said instruction set modifier register is coupled to said data bus and to one of said control lines.

Claim 8

The processor recited in claim 4 wherein said instruction set modifier register comprises at least one bistable logic means.

Claim 9

The processor recited in claim 4 wherein said instruction decoding and control circuit comprises: instruction decoding logic comprising a first plurality of conductors responsive to said instruction register, a second plurality of conductors intersecting said first plurality of conductors, first means responsive to the receipt of a first set of binary signals on said first plurality of conductors for causing a first group of binary signals to be generated over said second plurality of conductors, a third plurality of conductors intersecting said first plurality of conductors, second means responsive to the receipt of a second set of binary signals on said first plurality of conductors for causing a second group of binary signals to be generated over said third plurality of conductors, and instruction execution control logic responsive to said second and third plurality of conductors for activating said ones of said plurality of control lines.

Claim 10

In a processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an instruction representing an operation to be performed by said processor, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instruction, said processor further comprising: an instruction set modifier register having at least a first state and a second state each corresponding to a different instruction set, said instruction decoding and control circuit being responsive to said instruction set modifier register for generating a first set of control signals over said control lines in response to said first state of said instruction set modifier register and the storing of said instruction in said instruction register and generating a second set of control signals over said control lines in response to said second state of said instruction set modifier register and the storing of said instruction in said instruction register, said instruction set modifier register being coupled to said data bus and to one of said control lines, the state of said instruction set modifier register being set in accordance with the execution of a predetermined instruction by said processor.

Claim 11

In a processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an instruction representing an operation to be performed by said processor, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instruction, said processor further comprising: an instruction set modifier register having at least a first state and a second state each corresponding to a different instruction set, said instruction decoding and control circuit being responsive to said instruction set modifier register for generating a first set of control signals over said control lines in response to said first state of said instruction set modifier register and the storing of said instruction in said instruction register and generating a second set of control signals over said control lines in response to said second state of said instruction set modifier register and the storing of said instruction in said instruction register, said instruction set modifier register being coupled to said data bus and to one of said control lines, the state of said instruction set modifier register being set in accordance with the execution of a predetermined instruction by said processor.

Claim 12

The processor recited in claim 8 wherein said instruction set modifier register comprises at least one bistable logic means.

Claim 13

A processor comprising: a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, said instruction sets sharing in common at least one instruction representing an operation to be performed by said processor, said at least one instruction being represented by a different instruction word in each of said instruction sets, said instruction register generating a first set of binary signals in response to storing a first instruction word representation of said at least one instruction and generating a second set of binary signals in response to storing a second instruction word representation of said at least one instruction, an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction set modifier register generating a third set of binary signals representing a first one of said plurality of states and generating a fourth set of binary signals representing a second one of said plurality of states, instruction decoding logic comprising a first plurality of conductors responsive to said instruction register, a second plurality of conductors responsive to said instruction set modifier register, a third plurality of conductors intersecting said first and second plurality of conductors, a fourth plurality of conductors associated with selected ones of said third plurality of conductors and intersecting said first and second plurality of conductors, first means responsive to said first and third sets of binary signals for generating a first group of binary signals over said third plurality of conductors, second means responsive to said second and fourth sets of binary signals for generating a second group of binary signals over said fourth plurality of conductors, and instruction execution control logic having a plurality of control lines and controlling the operation of said plurality of registers and logic circuit by activating selecting ones of said control lines, said instruction execution control logic being responsive to said third and fourth plurality of conductors and comprising means for activating the same ones of said control lines in response to either of said first or second group of signals.

Claim 14

A processor comprising: a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, said instruction sets sharing in common at least one instruction representing an operation to be performed by said processor, said at least one instruction being represented by a different instruction word in each of said instruction sets, said instruction register generating a first set of binary signals in response to storing a first instruction word representation of said at least one instruction and generating a second set of binary signals in response to storing a second instruction word representation of said at least one instruction, an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction set modifier register generating a third set of binary signals representing a first one of said plurality of states and generating a fourth set of binary signals representing a second one of said plurality of states, instruction decoding logic comprising a first plurality of conductors responsive to said instruction register, a second plurality of conductors responsive to said instruction set modifier register, a third plurality of conductors intersecting said first and second plurality of conductors, a fourth plurality of conductors associated with selected ones of said third plurality of conductors and intersecting said first and second plurality of conductors, first means responsive to said first and third sets of binary signals for generating a first group of binary signals over said third plurality of conductors, second means responsive to said second and fourth sets of binary signals for generating a second group of binary signals over said fourth plurality of conductors, and instruction execution control logic having a plurality of control lines and controlling the operation of said plurality of registers and logic circuit by activating selecting ones of said control lines, said instruction execution control logic being responsive to said third and fourth plurality of conductors and comprising means for activating the same ones of said control lines in response to either of said first or second group of signals.

Claim 15

The processor recited in claim 10 wherein said means for activating comprises a plurality of OR-type logic gates.

Claim 16

The processor recited in claim 10 wherein said instruction set modifier register is coupled to said data bus and to one of said control lines and wherein the state of said instruction set modifier register is set in accordance with the execution of a predetermined instruction by said processor.

Claim 17

The processor recited in claim 10 wherein said instruction set modifier register comprises at least one bistable logic means.

Claim 18

A processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual instruction from one of a plurality of instructions from two or more instruction sets, said instruction representing an operation to be performed by said processor, an instruction decoding circuit responsive to said instruction register for decoding the contents of said instruction register, said instruction decoding circuit comprising at least a first set and a second set of decoding lines each corresponding to a different instruction set, an instruction set modifier register having at least a first state and a second state each corresponding to a different instruction set, said instruction decoding circuit being responsive to said instruction set modifier register for generating a first set of decoded signals over said first set of decoding lines in response to said first state of said instruction set modifier register and the storing of said instruction in said instruction register and generating a second set of decoded signals over said second set of decoding lines in response to said second state of said instruction set modifier register and the storing of said instruction in said instruction register, a plurality of logic means, each individually responsive to one of said first set of decoding lines and one of said second set of decoding lines and each generating a control input signal in response to a decoded signal received over either of said decoding lines, and a control circuit responsive to the control input signals generated by said plurality of logic means and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instruction.

Claim 19

A processor comprising a data bus for transmitting and receiving data, a plurality of registers and logic circuits including an instruction register coupled to said data bus for temporarily storing an individual instruction from one of a plurality of instructions from two or more instruction sets, said instruction representing an operation to be performed by said processor, an instruction decoding circuit responsive to said instruction register for decoding the contents of said instruction register, said instruction decoding circuit comprising at least a first set and a second set of decoding lines each corresponding to a different instruction set, an instruction set modifier register having at least a first state and a second state each corresponding to a different instruction set, said instruction decoding circuit being responsive to said instruction set modifier register for generating a first set of decoded signals over said first set of decoding lines in response to said first state of said instruction set modifier register and the storing of said instruction in said instruction register and generating a second set of decoded signals over said second set of decoding lines in response to said second state of said instruction set modifier register and the storing of said instruction in said instruction register, a plurality of logic means, each individually responsive to one of said first set of decoding lines and one of said second set of decoding lines and each generating a control input signal in response to a decoded signal received over either of said decoding lines, and a control circuit responsive to the control input signals generated by said plurality of logic means and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instruction.

Claim 20

The processor recited in claim 14 wherein said logic means comprise OR-type logic gates.

Claim 21

The processor recited in claim 14 wherein said instruction decoding circuit comprises additional decoding lines, and wherein said control circuit is also responsive to said additional decoding lines.

Claim 22

The processor recited in claim 14 wherein said instruction set modifier register comprises at least one bistable logic means.

Claim 23

The processor recited in claim 14 wherein said instruction set modifier register is coupled to said data bus and to one of said control lines and wherein the state of said instruction set modifier register is set in accordance with the execution of a predetermined instruction by said processor.