US6344401B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a stacked-die integrated circuit chip package on a water level
Assignee: Atmel Corp
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Filing: 2000-03-09
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Granted: 2002-02-05
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Expires: 2020-03-09
Abstract
Abstract A wafer level packaging method which produces a stacked dual/multiple die integrated circuit package. In the method, the wafer with the smaller sized dice of two wafers is processed through a metal redistribution process and then solder balls are attached. The wafer is then sawed into individual die size ball-grid array packages. On the wafer with the larger sized dice, a die attached adhesive material is deposited on the front of each die site location that is intended for the attachment of one of the die-sized BGA packages. The back side of the BGA die package is placed onto the adhesive material and is cured. A wirebonding operation connects the signals from the die-size BGA package to the circuits of the bottom die. A coating material, such as epoxy, is disposed on the wafer to cover the wirebond leads and the assembly is then cured. Then, the stacked-die wafer is singulated into individual stacked-die IC packages.
Inventors
- 👤 Ken M. Lam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:01
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/073; H10W72/075; H10W72/20; H10W72/29; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/59; H10W72/851; H10W72/853; H10W72/859; H10W72/874; H10W72/884; H10W90/20; H10W90/291; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/732; H10W90/751; H10W90/752
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
197 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and a second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size than the plurality of dice of the first wafer, each of the plurality of dice of the first and second wafers having a plurality of bonding pads disposed on a first surface thereof, attaching a plurality of interconnects to the plurality of bonding pads of the first surface of the plurality of dice of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice of the second wafer to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, connecting the plurality of bonding pads of the individual dice to the plurality of bonding pads of the plurality of dice of the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit packages.
Claim 2
Independent Claim
197 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and a second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size than the plurality of dice of the first wafer, each of the plurality of dice of the first and second wafers having a plurality of bonding pads disposed on a first surface thereof, attaching a plurality of interconnects to the plurality of bonding pads of the first surface of the plurality of dice of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice of the second wafer to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, connecting the plurality of bonding pads of the individual dice to the plurality of bonding pads of the plurality of dice of the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit packages.
Claim 3
Dependent Claim
59 words
The method of claim 1 , further comprising, before the step of attaching the plurality of interconnects to the plurality of bonding pads of the first surface of the plurality of dice of the second wafer, forming a metal redistribution layer on the first surface of the second wafer to form a plurality of wirebond pads and interconnect pads.
Claim 4
Dependent Claim
23 words
The method of claim 2 wherein the interconnects are attached to the interconnects pads on the metal redistribution layer of the second wafer.
Claim 5
Dependent Claim
27 words
The method of claim 2 wherein the plurality of wirebond pads of the individual dice are connected to the plurality of bonding pads of the first wafer.
Claim 6
Dependent Claim
37 words
The method of claim 1 wherein the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer is made by a plurality of bonding leads.
Claim 7
Dependent Claim
42 words
The method of claim 5 , further comprising, after the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, applying a coating material over the plurality of bonding leads.
Claim 8
Dependent Claim
11 words
The method of claim 6 wherein the coating material is epoxy.
Claim 9
Dependent Claim
40 words
The method of claim 1 , further comprising, after the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, testing the package structures on the first wafer.
Claim 10
Dependent Claim
16 words
The method of claim 1 wherein the plurality of interconnects are a plurality of solder balls.
Claim 11
Dependent Claim
19 words
The method of claim 1 wherein the individual dice are attached to the first wafer by an adhesive material.
Claim 12
Independent Claim
199 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size than the plurality of dice of the first wafer, each of the plurality of dice having a plurality of bonding pads disposed on a first surface thereof, forming a metal redistribution layer on a first surface of the second wafer to form a plurality of wirebond pads and interconnect pads, attaching a plurality of interconnects to the interconnect pads of the metal redistribution layer of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit chip packages.
Claim 13
Independent Claim
199 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size than the plurality of dice of the first wafer, each of the plurality of dice having a plurality of bonding pads disposed on a first surface thereof, forming a metal redistribution layer on a first surface of the second wafer to form a plurality of wirebond pads and interconnect pads, attaching a plurality of interconnects to the interconnect pads of the metal redistribution layer of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit chip packages.
Claim 14
Dependent Claim
37 words
The method of claim 11 wherein the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer is made by a plurality of bonding leads.
Claim 15
Dependent Claim
42 words
The method of claim 12 , further comprising, after the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, applying a coating material over the plurality of bonding leads.
Claim 16
Dependent Claim
11 words
The method of claim 13 wherein the coating material is epoxy.
Claim 17
Dependent Claim
40 words
The method of claim 11 , further comprising, after the step of connecting the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, testing the package structures on the first wafer.
Claim 18
Dependent Claim
16 words
The method of claim 11 wherein the plurality of interconnects are a plurality of solder balls.
Claim 19
Dependent Claim
19 words
The method of claim 11 wherein the individual dice are attached to the first wafer by an adhesive material.
Claim 20
Independent Claim
225 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size then the plurality of dice of the first wafer, each of the plurality of dice having a plurality of bonding pads disposed on a first surface thereof, forming a metal redistribution layer on a first surface of the second wafer to form a plurality of wirebond pads and interconnect pads, attaching a plurality of solder balls to the interconnect pads of the metal redistribution layer of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, using a plurality of bonding leads to connect the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, applying a coating material over the plurality of bonding leads, testing the package structures on the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit chip packages.
Claim 21
Independent Claim
225 words
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising: providing a first semiconductor wafer and second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size then the plurality of dice of the first wafer, each of the plurality of dice having a plurality of bonding pads disposed on a first surface thereof, forming a metal redistribution layer on a first surface of the second wafer to form a plurality of wirebond pads and interconnect pads, attaching a plurality of solder balls to the interconnect pads of the metal redistribution layer of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, using a plurality of bonding leads to connect the plurality of wirebond pads of the individual dice to the plurality of bonding pads of the first wafer, applying a coating material over the plurality of bonding leads, testing the package structures on the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit chip packages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-04 | 2005-08-06 | 2006-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-04 | 2009-08-06 | 2010-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-04 | 2013-08-06 | 2014-02-05 | $7700.00 | Window Closed / Lapsed |