Gate-voltage controlled electrostatic discharge protection circuit

Claim 1

An ESD protection circuit coupled between an input pad and an integrated circuit device, the integrated circuit device having an inverter coupled to its internal circuit for the purpose of protecting the integrated circuit device against ESD stress, the ESD protection circuit comprising: a resistor having a first end connected to a common node connected to the input pad and a second end connected to the input end of the inverter; a PMOS transistor whose source is connected to a first power line and whose drain is connected to the common node; a first potential drop subcircuit having a positive end connected to the gate of the PMOS transistor and a negative end connected to the common node, wherein the first potential drop subcircuit switches into the conductive state when a negative ESD voltage lower in magnitude than a predetermined level is applied to the input pad, causing the PMOS transistor to be switched into the conductive state, and the first potential drop subcircuit further reducing the negative ESD voltage; an NMOS transistor whose source is connected to a second power line and whose drain is connected to the common node; and a second potential drop subcircuit having a positive end connected to the common node and a negative end connected to the gate of the NMOS transistor, wherein the second potential drop subcircuit is switched into the conductive state when a positive ESD voltage higher in magnitude than a predetermined level is applied to the input pad, causing the NMOS transistor to be switched into the conductive state, and the second potential drop subcircuit further reducing the positive ESD voltage.