Patent US6429533B1 successfully refreshed from Google Patents.
Patent US5406394A successfully refreshed from Google Patents.
Patent US6337240B1 successfully refreshed from Google Patents.
US6337240B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating an embedded dynamic random access memory
Assignee: FOOTHILLS IP LLC
•
Filing: 1999-01-25
•
Granted: 2002-01-08
•
Expires: 2019-01-25
Abstract
Abstract A method for fabricating an embedded dynamic random access memory (DRAM) is provided. The method contains implanting ions onto the substrate at a DRAM active area and a logic circuit with different dopant concentration. A thermal oxidation process is performed to form a DRAM gate oxide layer with a greater thickness than that of a logic gate oxide layer. A DRAM MOS transistor is formed at a DRAM region and a logic MOS transistor is formed at a logic region. The DRAM MOS transistor has a polycide gate structure. The logic transistor has a first self-aligned silicide (Salicide) layer on its gate structure, and a second Salicide on its interchangeable source/drain region. A dielectric layer is formed over the substrate. A contact opening is formed in the dielectric layer by patterning the dielectric layer to expose the interchangeable source/drain region of the DRAM transistor. A stack capacitor is formed on the dielectric layer.
Inventors
- 👤 Chih-Hsun Chu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:10
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10B12/02; H10B12/05; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
372 words
A method for fabricating an embedded dynamic random access memory (DRAM) on a semiconductor substrate, having a DRAM region and a periphery region, the method comprising: forming a first oxide layer and a second oxide layer on the substrate respectively at the DRAM region and the periphery region, wherein a thickness of the first oxide layer is different from a thickness of the second oxide layer; forming a polysilicon layer over the substrate; sequentially forming a silicide layer and a cap layer on the polysilicon layer at the DRAM region; patterning the cap layer, the silicide layer, the polysilicon layer, and the first oxide layer to form a first gate structure at the DRAM region, and simultaneously patterning the polysilicon layer and the second oxide layer to form a second semi-gate structure at the periphery region; implanting ions onto the substrate, using the first gate structure and the second semi-gate structure as a mask, to form a first lightly doped region in the substrate at the DRAM region and a second lightly doped region in the substrate at the periphery region; forming a first spacer on each sidewall of the first gate structure, and a second spacer on each sidewall on each sidewall of second semi-gate structure; implanting ions onto the substrate, using the first gate structure, the first spacer, the second semi-gate structure, and the second spacer as a mask, to form a first heavily doped region in the substrate at the DRAM region and a second heavily doped region in the substrate at the periphery region, wherein the first lightly doped region and the first heavily doped region serve as a first interchangeable source/drain region, and the second lightly doped region and the second heavily doped region serve as a second interchangeable source/drain region, forming an insulating layer over the substrate at the DRAM region; performing a self-aligned silicide (Salicide) process to form a first Salicide layer on the second semi-gate structure and a second Salicide layer on the second interchangeable source/drain region, wherein the first Salicide layer and the second semi-gate structure form a second gate structure at the periphery region; and forming a capacitor, which is electrically coupled to the first interchangeable source/drain region at the DRAM region.
Claim 2
Independent Claim
372 words
A method for fabricating an embedded dynamic random access memory (DRAM) on a semiconductor substrate, having a DRAM region and a periphery region, the method comprising: forming a first oxide layer and a second oxide layer on the substrate respectively at the DRAM region and the periphery region, wherein a thickness of the first oxide layer is different from a thickness of the second oxide layer; forming a polysilicon layer over the substrate; sequentially forming a silicide layer and a cap layer on the polysilicon layer at the DRAM region; patterning the cap layer, the silicide layer, the polysilicon layer, and the first oxide layer to form a first gate structure at the DRAM region, and simultaneously patterning the polysilicon layer and the second oxide layer to form a second semi-gate structure at the periphery region; implanting ions onto the substrate, using the first gate structure and the second semi-gate structure as a mask, to form a first lightly doped region in the substrate at the DRAM region and a second lightly doped region in the substrate at the periphery region; forming a first spacer on each sidewall of the first gate structure, and a second spacer on each sidewall on each sidewall of second semi-gate structure; implanting ions onto the substrate, using the first gate structure, the first spacer, the second semi-gate structure, and the second spacer as a mask, to form a first heavily doped region in the substrate at the DRAM region and a second heavily doped region in the substrate at the periphery region, wherein the first lightly doped region and the first heavily doped region serve as a first interchangeable source/drain region, and the second lightly doped region and the second heavily doped region serve as a second interchangeable source/drain region, forming an insulating layer over the substrate at the DRAM region; performing a self-aligned silicide (Salicide) process to form a first Salicide layer on the second semi-gate structure and a second Salicide layer on the second interchangeable source/drain region, wherein the first Salicide layer and the second semi-gate structure form a second gate structure at the periphery region; and forming a capacitor, which is electrically coupled to the first interchangeable source/drain region at the DRAM region.
Claim 3
Dependent Claim
78 words
The method of claim 1 , wherein the step of forming the first oxide layer an the second oxide layer further comprises: performing an ion implantation process to dope the substrate at the DRAM region with a first dopant concentration, and the periphery region with a second dopant concentrations, wherein the first dopant concentration is different from the second dopant concentration; and performing a thermal oxidation process to form the first oxide layer and the second oxide layer.
Claim 4
Dependent Claim
47 words
The method of claim 2 , wherein the first dopant concentration is less than the second dopant concentration so that the thickness of the first oxide layer is greater than the thickness of the second oxide layer, in which the first dopant concentration can also be zero.
Claim 5
Dependent Claim
22 words
The method of claim 2 , wherein the step of performing the ion implantation process to dope the substrate comprises nitrogen ions.
Claim 6
Dependent Claim
22 words
The method of claim 1 , wherein the silicide layer comprises tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, or cobalt silicide.
Claim 7
Dependent Claim
19 words
The method of claim 1 , wherein the step of forming the insulation layer comprises chemical vapor deposition (CVD).
Claim 8
Dependent Claim
67 words
The method of claim 1 , wherein the step of performing the Salicide process further comprises: forming a metal layer over the substrate; performing a first annealing process to trigger a reaction between the metal layer and silicon material in the substrate at their interface to form the first Salicide layer and the second Salicide layer; and removing a remaining portion of the metal layer without reaction.
Claim 9
Dependent Claim
18 words
The method of claim 7 , wherein the first annealing process comprises a rapid thermal annealing (RTA) process.
Claim 10
Dependent Claim
32 words
The method of claim 7 , wherein the first annealing process comprises a rapid thermal annealing (RTA) process at a temperature of about 700° C. for a duration of about 30 seconds.
Claim 11
Dependent Claim
46 words
The method of claim 9 , wherein after the step of removing a remaining portion of metal layer without reaction, the Salicide process further comprises performing a second annealing process so as to have a better quality of the first Salicide layer and the second Salicide.
Claim 12
Dependent Claim
31 words
The method of claim 9 , wherein the second annealing process comprises a RTA process at a temperature of about greater than 750° C. for a duration of about 10 minutes.
Claim 13
Dependent Claim
23 words
The method of claim 7 , wherein the step of removing the remaining portion of the metal layer without reaction comprises wet etching.
Claim 14
Dependent Claim
39 words
The method of claim 7 , wherein the step of removing the remaining portion of the metal layer without reaction comprises wet etching with an acid solution mixed by hydrogen peroxide (H 2 O 2 ) and ammonium hydroxide.
Claim 15
Dependent Claim
19 words
The method of claim 7 , wherein the metal layer comprises titanium, tungsten, cobalt, tantalum, nickel, molybdenum or palladium.
Claim 16
Dependent Claim
26 words
The method of claim 1 , wherein the silicide layer at the DRAM region comprises tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, or cobalt silicide.
Claim 17
Dependent Claim
16 words
The method of claim 1 , wherein the cap layer comprises silicon nitride or silicon oxide.
Claim 18
Dependent Claim
13 words
The method of claim 1 , wherein the polysilicon layer comprises doped polysilicon.
Claim 19
Dependent Claim
19 words
The method of claim 1 , wherein the step of forming the polysilicon further comprises doping dopants in situ.
Claim 20
Dependent Claim
18 words
The method of claim 1 , wherein the step for forming the capacitor comprises forming a stack capacitor.
Claim 21
Dependent Claim
18 words
The method of claim 1 , wherein the step for forming the capacitor comprises forming a trench capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-07 | 2005-07-09 | 2006-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-07 | 2009-07-09 | 2010-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-07 | 2013-07-09 | 2014-01-08 | $7700.00 | Window Closed / Lapsed |