US6323910B1
Expired / Lapsed
US
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Method and apparatus for producing high-fidelity images by synchronous phase coherent digital image acquisition
Assignee: CLARK RESEARCH AND DEVELOPMENT Inc
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Filing: 1998-03-26
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Granted: 2001-11-27
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Expires: 2018-03-26
Abstract
Abstract An apparatus and method for synchronizing sampling of a video signal to a video synchronization signal of the video signal are provided. The frequency-divided output of an oscillator (or other controllable frequency source) is applied as one input to a phase detector, while the other input to the phase detector is supplied by the video synchronizing signals. The error signal voltage output of the phase detector is applied to correct the frequency, and thereby the phase, of the oscillator output through a dynamically-tuned phase-locked loop filter until the phases of the two input signals are in perfect agreement and no error voltage is produced. After a delay for this phase correction, during which time all video amplification is suspended, an output of the oscillator is then applied to sample the image without the presence of phase disparities while video amplification is restored. Full dynamic range digital acquisition then proceeds with extremely high accuracy at any desired resolution. An apparatus and method are provided for achieving such operation.
Inventors
- 👤 William T. Clark, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 55
Claim 1
Independent Claim
91 words
An apparatus for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said apparatus comprising: a phase corrector, responsive to said video synchronization signal and capable of adjusting a phase of a sampling clock signal in order to coincide with a phase of said video synchronization signal; and a first delay element to delay said sampling of said video signal at least until said phase corrector has adjusted the phase of said sampling clock signal to coincide with a phase of said video synchronization signal.
Claim 2
Independent Claim
91 words
An apparatus for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said apparatus comprising: a phase corrector, responsive to said video synchronization signal and capable of adjusting a phase of a sampling clock signal in order to coincide with a phase of said video synchronization signal; and a first delay element to delay said sampling of said video signal at least until said phase corrector has adjusted the phase of said sampling clock signal to coincide with a phase of said video synchronization signal.
Claim 3
Dependent Claim
15 words
The apparatus of claim 1 , wherein said phase corrector comprises a phase-locked loop arrangement.
Claim 4
Dependent Claim
82 words
The apparatus of claim 2 , wherein said phase-locked loop arrangement comprises a phase detector capable of detecting the extent of phase difference between the phase of said sampling clock signal and the phase of said video synchronization signal and capable of providing an output error signal, said output error signal communicating the extent of said phase difference between said sampling clock signal and said video synchronization signal and communicating adjustment to be applied to the phase of said sampling clock signal.
Claim 5
Dependent Claim
87 words
The apparatus of claim 2 , wherein said phase-locked loop arrangement comprises, a phase detector configured to compare the phase of said sampling clock signal to the phase of said video synchronization signal and to provide an output error signal representing the extent of a phase difference between said sampling clock signal and said video synchronization signal, and an oscillator communicating with said output error signal in such a manner that said sampling clock signal generated by said oscillator is adjusted according to said output error signal.
Claim 6
Dependent Claim
39 words
The apparatus of claim 4 , wherein said oscillator is a voltage-controlled oscillator and wherein said output error signal is a voltage communicating the extent of said phase difference between said sampling clock signal and said video synchronization signal.
Claim 7
Dependent Claim
62 words
The apparatus of claim 4 , wherein said oscillator is a fixed-frequency oscillator which generates said sampling clock signal, and wherein said sampling clock signal communicates with a phase shifter, and said phase shifter communicates with said output error signal in such manner that said phase shifter adjusts the phase of said sampling clock signal in accordance with said output error signal.
Claim 8
Dependent Claim
24 words
The apparatus of claim 4 , wherein said phase-locked loop arrangement further comprises a loop filter connected between said oscillator and said phase detector.
Claim 9
Dependent Claim
26 words
The apparatus of claim 7 , wherein said loop filter comprises: a capacitive element; and an hysteresis controlling resistance connected in parallel to said capacitive element.
Claim 10
Dependent Claim
13 words
The apparatus of claim 8 , wherein said hysteresis controlling resistance is variable.
Claim 11
Dependent Claim
70 words
The apparatus of claim 7 , wherein said loop filter comprises: a settling resistance communicating with said output error signal between said phase detector and said oscillator; a damping resistance communicating with said output error signal between said phase detector, said oscillator and ground; a capacitance communicating with said output error signal between said phase detector and said oscillator; and an hysteresis controlling resistance connected in parallel with said capacitance.
Claim 12
Dependent Claim
13 words
The apparatus of claim 10 , wherein said hysteresis controlling resistance is variable.
Claim 13
Dependent Claim
107 words
The apparatus of claim 4 , wherein said phase-locked loop arrangement further comprises a frequency divider communicating between said sampling clock signal and said phase detector, said frequency divider being arranged so as to divide a frequency of said sampling clock signal to produce a frequency associated with said video synchronization signal, thereby providing a frequency divided version of said sampling clock signal, said frequency divided version of said sampling clock signal being applied to said phase detector so that said phase detector detects the extent of phase difference between said frequency divided version of the sampling clock signal and the phase of said video synchronization signal.
Claim 14
Dependent Claim
79 words
The apparatus of claim 1 , further comprising a gate communicating with said first delay element and capable of communicating said sampling clock signal to said video signal, said gate being responsive to said first delay element and being arranged so as to prevent application of said sampling clock signal to said video signal at least until said phase corrector has adjusted a phase of said sampling clock signal to coincide with a phase of said video synchronization signal.
Claim 15
Dependent Claim
92 words
The apparatus of claim 13 further comprising a video gate communicating with said first delay element and connectable to a video output line which carries said video signal to a sampling unit which samples said video signal according to said sampling clock signal, said video gate being responsive to said first delay element and arranged so as to suspend said video signal from said video output line at least until said phase corrector has adjusted the phase of said sampling clock signal to coincide with a phase of said video synchronization signal.
Claim 16
Dependent Claim
49 words
The apparatus of claim 14 , wherein said video gate is responsive to said first delay element and is capable of grounding the video output line at least until the phase of said sampling clock signal has been adjusted to coincide with a phase of said video synchronization signal.
Claim 17
Dependent Claim
24 words
The apparatus of claim 1 , wherein said first delay element comprises a monostable differentiator triggered by an edge of said video synchronization signal.
Claim 18
Dependent Claim
24 words
The apparatus of claim 1 , wherein said first delay element comprises a monostable multivibrator triggered by an edge of said video synchronization signal.
Claim 19
Dependent Claim
25 words
The apparatus of claim 1 , wherein said first delay element comprises a digital frequency divider triggered by an edge of said video synchronization signal.
Claim 20
Dependent Claim
71 words
The apparatus of claim 1 , wherein said video synchronization signal is a horizontal synchronization signal, and said apparatus further comprises: a second delay element responsive to a vertical synchronization signal, said second delay element being arranged so as to prevent sampling of said video signal at least until said phase corrector has adjusted a phase of said sampling clock signal to coincide with the phase of said horizontal synchronization signal.
Claim 21
Dependent Claim
88 words
The apparatus of claim 19 , further comprising a video gate communicating with said first delay element and connectable to a video output line which carries said video signal to a sampling unit which samples said video signal in accordance with said sampling clock signal, said video gate being responsive to said first delay element and arranged so as to suspend said video signal from said video output line at least until the phase of said sampling clock signal coincides with the phase of said horizontal synchronization signal.
Claim 22
Dependent Claim
91 words
The apparatus of claim 19 , further comprising a first gate communicating with said first delay element and connectable to a sampling unit which samples said video signal in accordance with said sampling clock signal, said first gate being responsive to said first delay element and being arranged so as to delay, in accordance with said horizontal synchronization signal, application of said sampling clock signal to said sampling unit at least until the phase of said sampling clock signal is adjusted to coincide with the phase of said horizontal synchronization signal.
Claim 23
Dependent Claim
79 words
The apparatus of claim 21 , further comprising a second gate communicating with said second delay element and connectable to said sampling unit, said second gate being responsive to said second delay element and being arranged so as to delay, in accordance with said vertical synchronization signal, application of said sampling clock signal to said sampling unit at least until the phase of said sampling clock signal is adjusted to coincide with the phase of said horizontal synchronization signal.
Claim 24
Dependent Claim
79 words
The apparatus of claim 20 , further comprising a video gate communicating with said first delay element and connectable to a video output line which carries said video signal to said sampling unit, said video gate being responsive to said first delay element and arranged so as to suspend said video signal from said video output line at least until the phase of said sampling clock signal is adjusted to coincide with the phase of said horizontal synchronization signal.
Claim 25
Dependent Claim
48 words
The apparatus of claim 23 , further comprising an inverter communicating with said first gate and said video gate and arranged so that when said first gate is open said video gate is closed and so that when said first gate is closed said video gate is open.
Claim 26
Dependent Claim
148 words
The apparatus of claim 1 , wherein said phase corrector comprises, (a) a phase-locked loop arrangement comprising, (i) a phase detector capable of comparing the phase of said sampling clock signal to the phase of said video synchronization signal and capable of providing an output error signal indicating presence of a phase difference between said sampling clock signal and said video synchronization signal, and (ii) an oscillator communicating with said output error signal, said oscillator being arranged so as to generate said sampling clock signal in a manner dependent upon said output error signal, and (b) a frequency divider communicating with said sampling clock signal from said oscillator, said frequency divider being arranged so as to divide a frequency of said sampling clock signal by one of a plurality of selectable values to generate a frequency divided version of said sampling clock signal and a respective sampling rate.
Claim 27
Dependent Claim
108 words
The apparatus of claim 25 , wherein said phase-locked loop arrangement further comprises an additional frequency divider communicating with said sampling clock signal and said phase detector, said additional frequency divider being arranged so as to divide the frequency of said sampling clock signal to a frequency associated with said video synchronization signal, thereby providing an additional frequency divided version of said sampling clock signal, said additional frequency divided version of said sampling clock signal being applied to said phase detector so that said phase detector compares the phase of said additional frequency divided version of the sampling clock signal to the phase of said video synchronization signal.
Claim 28
Independent Claim
67 words
A method for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said method comprising: adjusting a phase of a sampling clock signal to coincide with a phase of said video synchronization signal; and delaying said sampling of said video signal at least until the phase of said sampling clock signal has coincided with the phase of said video synchronization signal.
Claim 29
Independent Claim
67 words
A method for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said method comprising: adjusting a phase of a sampling clock signal to coincide with a phase of said video synchronization signal; and delaying said sampling of said video signal at least until the phase of said sampling clock signal has coincided with the phase of said video synchronization signal.
Claim 30
Dependent Claim
25 words
The method of claim 27 , wherein said adjusting comprises applying said sampling clock signal and said video synchronization signal into a phase-locked loop arrangement.
Claim 31
Dependent Claim
48 words
The method of claim 28 , wherein said adjusting comprises, comparing the phase of said sampling clock signal to the phase of said video synchronization signal and providing an output error signal representing the extent of phase difference between said sampling clock signal and said video synchronization signal.
Claim 32
Dependent Claim
24 words
The method of claim 29 , wherein said adjusting comprises modifying said sampling clock signal in a manner dependent upon said output error signal.
Claim 33
Dependent Claim
54 words
The method of claim 30 , wherein said modifying is carried out by a voltage-controlled oscillator which generates said sampling clock signal in accordance with said output error signal, wherein said output error signal is a voltage representing the extent of said phase difference between said sampling clock signal and said video synchronization signal.
Claim 34
Dependent Claim
68 words
The method of claim 30 , wherein said modifying is carried out by a phase shifter which, in accordance with said output error signal, shifts the phase of said sampling clock signal, which sampling clock signal is generated by a fixed-frequency oscillator and wherein said output error signal is a voltage representing the extent of said phase difference between said sampling clock signal and said video synchronization signal.
Claim 35
Dependent Claim
23 words
The method of claim 31 , wherein said modifying further comprises a step of filtering said output error signal using a loop filter.
Claim 36
Dependent Claim
33 words
The method of claim 33 , wherein said step of filtering comprises a step of controlling hysteresis by connecting a hysteresis controlling resistance in parallel to a capacitive element of the loop filter.
Claim 37
Dependent Claim
20 words
The method of claim 34 , wherein said controlling hysteresis comprises dynamically establishing a value of said hysteresis controlling resistance.
Claim 38
Dependent Claim
65 words
The method of claim 30 , wherein, said adjusting further comprises dividing a frequency of said sampling clock signal to a frequency associated with said video synchronization signal, to thereby provide a frequency divided version of said sampling clock signal, and said comparing comprises comparing a phase of said frequency divided version of the sampling clock signal to a phase of said video synchronization signal.
Claim 39
Dependent Claim
52 words
The method of claim 27 , wherein said delaying comprises preventing sampling of said video signal by blocking application of said sampling clock signal to a sampling unit which samples said video signal at least until a phase of said sampling clock signal coincides with a phase of said video synchronization signal.
Claim 40
Dependent Claim
37 words
The method of claim 37 , further comprising suspending application of said video signal to said sampling unit at least until the phase of said sampling clock signal coincides with a phase of said video synchronization signal.
Claim 41
Dependent Claim
43 words
The method of claim 38 , wherein said suspending comprises grounding a video output line which carries said video signal to the sampling unit, at least until the phase of said sampling clock signal coincides with a phase of said video synchronization signal.
Claim 42
Dependent Claim
57 words
The method of claim 27 , wherein said video synchronization signal is a horizontal synchronization signal, said method further comprising delaying application of said sampling clock signal to said video signal in response to a vertical synchronization signal at least until a phase of said sampling clock signal coincides with a phase of said horizontal synchronization signal.
Claim 43
Dependent Claim
37 words
The method of claim 39 , further comprising suspending application of said video signal to said sampling unit at least until the phase of said sampling clock signal coincides with a phase of said horizontal synchronization signal.
Claim 44
Dependent Claim
43 words
The method of claim 41 , wherein said suspending comprises grounding a video output line which carries said video signal to the sampling unit at least until the phase of said sampling clock signal coincides with a phase of said horizontal synchronization signal.
Claim 45
Dependent Claim
55 words
The method of claim 27 , further comprising, frequency dividing said sampling clock signal to provide a frequency divided version of said sampling clock signals, and applying said frequency divided version of said sampling clock signal to a sampling unit that samples said video signal at a sampling rate determined by said frequency divided version.
Claim 46
Dependent Claim
27 words
The method of claim 43 , further comprising selectively varying a value by which said sampling clock signal is frequency divided to thereby provide different sampling resolutions.
Claim 47
Dependent Claim
67 words
The method of claim 43 , wherein said adjusting further comprises dividing a frequency of said sampling clock signal to a frequency associated with said video synchronization signal, to thereby provide an additional frequency divided version of said sampling clock signals, and said comparing comprises comparing a phase of said additional frequency divided version of the sampling clock signal to the phase of said video synchronization signal.
Claim 48
Dependent Claim
102 words
The method of claim 27 , further comprising establishing a delay period for said delaying, said establishing comprising, registering a first reception of a stable image pattern using said adjusting and delaying, registering a second reception of said stable image pattern using said adjusting and delaying, subtracting one of said first and second receptions from the other of said first and second receptions to generate a differential image representing differences between said first and second receptions, and adjusting said delay period and repeating said registering and subtracting until said differential image indicates absence of said differences between said first and second receptions.
Claim 49
Dependent Claim
106 words
The method of claim 46 , wherein said adjusting of said delay period comprises, applying said sampling clock signal and said video synchronization signal into a phase-locked loop arrangement, comparing the phase of said sampling clock signal to a phase of said video synchronization signal, providing an output error signal representing the extent of phase difference between said sampling clock signal and said video synchronization signals, filtering said output error signal using a loop filter, wherein said filtering includes controlling hysteresis by connecting a hysteresis controlling resistance in parallel to a capacitive element of the loop filter, and varying the resistance of the hysteresis controlling resistance.
Claim 50
Independent Claim
124 words
An apparatus for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said apparatus comprising: a phase corrector, responsive to said video synchronization signal and capable of adjusting a phase of a sampling clock signal in order to coincide with a phase of said video synchronization signal; and a first delay element to delay said sampling of said video signal at least until said phase corrector has adjusted the phase of said sampling clock signal to coincide with a phase of said video synchronization signal, wherein said phase corrector is configured as a phase-locked loop containing a loop filter, said loop filter including a capacitive element and a hysteresis controlling resistance connected in parallel to said capacitive element.
Claim 51
Independent Claim
124 words
An apparatus for synchronizing sampling of a video signal to a video synchronization signal of said video signal, said apparatus comprising: a phase corrector, responsive to said video synchronization signal and capable of adjusting a phase of a sampling clock signal in order to coincide with a phase of said video synchronization signal; and a first delay element to delay said sampling of said video signal at least until said phase corrector has adjusted the phase of said sampling clock signal to coincide with a phase of said video synchronization signal, wherein said phase corrector is configured as a phase-locked loop containing a loop filter, said loop filter including a capacitive element and a hysteresis controlling resistance connected in parallel to said capacitive element.
Claim 52
Dependent Claim
65 words
The apparatus of claim 48 , wherein said phased-locked loop further includes a phase detector coupled to said loop filter, said phase detector being capable of comparing the phase of said sampling clock signal to the phase of said video synchronization signal and generating an output error signal representing the extent of a phase difference between said sampling clock signal and said video synchronization signal.
Claim 53
Dependent Claim
42 words
The apparatus of claim 49 , wherein said phased-locked loop further includes an oscillator coupled to said loop filter, said oscillator configured to communicate with said output error signal to adjust the phase of said sampling clock signal generated by said oscillator.
Claim 54
Dependent Claim
46 words
The apparatus of claim 50 , wherein said loop filter further includes, a settling resistance communicating with said output error signal between said phase detector and said oscillator, and a damping resistance communicating with said output error signal between said phase detector, said oscillator, and ground.
Claim 55
Dependent Claim
13 words
The apparatus of claim 51 , wherein said hysteresis controlling resistance is variable.
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