US5886582A
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Enabling clock signals with a phase locked loop (PLL) lock detect circuit
Assignee: Cypress Semiconductor Corp
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Filing: 1996-08-07
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Granted: 1999-03-23
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Expires: 2016-08-07
Abstract
Abstract A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.
Inventors
- 👤 Galen E. Stansell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:48
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03L7/08; H03L7/085; H03L7/095; H03L7/089; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
64 words
A method of operating a clock signal generator comprising the step of: generating a lock signal in response to (i) a window signal and (ii) one or more control signals; and generating an output clock signal in response to (i) an input clock signal and (ii) said lock signal, wherein said lock signal corresponds to a lock state of a phase locked loop (PLL).
Claim 2
Independent Claim
64 words
A method of operating a clock signal generator comprising the step of: generating a lock signal in response to (i) a window signal and (ii) one or more control signals; and generating an output clock signal in response to (i) an input clock signal and (ii) said lock signal, wherein said lock signal corresponds to a lock state of a phase locked loop (PLL).
Claim 3
Dependent Claim
41 words
The method of claim 1 wherein said step of generating the output clock signal includes the substep of: blanking the output clock signal when the lock signal is in an inactive state indicative of a condition where the PLL is unlocked.
Claim 4
Dependent Claim
45 words
The method of claim 1 wherein said step of generating the output clock signal includes the substep of: generating the output clock signal in a valid state when the lock signal is in an active state indicative of a condition where the PLL is locked.
Claim 5
Dependent Claim
65 words
The method of claim 1 wherein said step of generating the output clock signal includes the substep of: disjunctively combining the input clock signal and the lock signal so that when the lock signal is in an inactive state the output clock signal is blanked and when the lock signal is in an active state the output clock signal is generated in a valid state.
Claim 6
Dependent Claim
106 words
The method of claim 1 further comprising the step of: synchronizing the lock signal with respect to the input clock signal to generate a synchronized lock signal to thereby prevent generation of an initial foreshortened pulse portion of the output clock signal; and wherein said step of generating the output clock signal includes the substep of disjunctively combining the input clock signal and the synchronized lock signal so that when the synchronized lock signal is in an inactive state the output clock signal is blanked and when the synchronized lock signal is in an active state the output clock signal is generated in a valid state.
Claim 7
Dependent Claim
40 words
The method of claim 1 further comprising the steps of: applying an input reference signal to the PLL; and, generating the lock signal when an output reference signal of the PLL is phase locked relative to the input reference signal.
Claim 8
Dependent Claim
15 words
The method of claim 6 wherein the output reference signal defines the input clock signal.
Claim 9
Dependent Claim
80 words
The method of claim 6 further including the steps of: varying the input reference signal to the PLL to thereby effect frequency slewing in the output reference signal; generating the lock signal in an inactive state when the output reference signal of the PLL is out-of-lock relative to the input reference signal; and, wherein said step of generating the output clock signal includes the substep of blanking the output clock signal when the lock signal is in the inactive state.
Claim 10
Dependent Claim
131 words
The method of claim 1 further comprising the steps of: applying an input reference signal to the PLL; generating the lock signal when an output reference signal of the PLL is outside of a predetermined tolerance defined by said window signal; synchronizing the lock signal with respect to the input clock signal to generate a synchronized lock signal, said output reference signal defining the input clock signal; and, wherein said step of generating said output clock signal includes the substep of disjunctively combining the input clock signal and the synchronized lock signal so that when the synchronized lock signal is in an inactive state the output clock signal is blanked and when the synchronized lock signal is in an active state the output clock signal is generated in a valid state.
Claim 11
Dependent Claim
95 words
The method of claim 1 wherein the PLL is a primary PLL, said method further including the steps of: applying an input reference signal to the primary PLL and a secondary PLL; generating a power-on-reset signal when a secondary PLL output reference signal is phase locked to the input reference signal; generating the lock signal in an active state when the primary PLL output reference signal is phase locked to the input reference signal and the power-on-reset signal is in an active state; and, maintaining the lock signal in the active state while frequency slewing.
Claim 12
Dependent Claim
82 words
A clock circuit comprising: means for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and, means responsive to an input clock signal for generating an output clock signal according to a control signal corresponding to said lock signal.
Claim 13
Dependent Claim
82 words
A clock circuit comprising: means for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and, means responsive to an input clock signal for generating an output clock signal according to a control signal corresponding to said lock signal.
Claim 14
Dependent Claim
36 words
The clock circuit of claim 11 further including: means for synchronizing said lock signal with respect to the input clock signal to generate a synchronized lock signal wherein said synchronized lock signal defines said control signal.
Claim 15
Dependent Claim
50 words
The clock circuit of claim 12 wherein said lock signal generating means includes a lock detector for generating the lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal.
Claim 16
Dependent Claim
33 words
The clock circuit of claim 12 wherein said output clock signal generating means includes an AND gate having a pair of input terminals for receiving said control signal and said input clock signal.
Claim 17
Dependent Claim
49 words
The clock circuit of claim 12 wherein said sychronizing means includes a D-type flip flop having a data input terminal for receiving said lock signal, a clock terminal for receiving said input clock signal, and a data output terminal for outputting said sychronized lock signal defining said control signal.
Claim 18
Dependent Claim
174 words
The clock circuit of claim 12 wherein said PLL is a primary PLL, said output reference signal is a primary PLL output reference signal, said primary PLL including an output terminal for generating a primary lock indicative signal, and said lock signal generating means comprises a primary lock detector responsive to said primary lock indicative signal, said clock circuit further including: a secondary PLL responsive to said input reference signal for generating a secondary PLL output reference signal and a secondary lock indicative signal on respective output terminals thereof; and, a secondary lock detector responsive to said secondary lock indicative signal for generating a power-on-reset signal indicative of a lock state of said secondary PLL; wherein said primary lock detector is configurable to generate said lock signal in an active state when said primary PLL output reference signal is phase locked to said input reference signal and said power-on-reset signal is in an active state; and, wherein said primary PLL includes means for maintaining said lock signal in said active state while frequency slewing.
Claim 19
Dependent Claim
157 words
A clock circuit comprising: a lock detector having an output terminal for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and, a logic gate having a first input terminal for receiving an input clock signal and a second input terminal for receiving a control signal corresponding to said lock signal, said logic gate having an output terminal for generating an output clock signal in a valid state when said control signal is in an active state indicative of a lock state where said PLL is locked, said logic gate blanking said output clock signal when said control signal is in an inactive state indicative of a lock state where said PLL is unlocked.
Claim 20
Dependent Claim
157 words
A clock circuit comprising: a lock detector having an output terminal for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and, a logic gate having a first input terminal for receiving an input clock signal and a second input terminal for receiving a control signal corresponding to said lock signal, said logic gate having an output terminal for generating an output clock signal in a valid state when said control signal is in an active state indicative of a lock state where said PLL is locked, said logic gate blanking said output clock signal when said control signal is in an inactive state indicative of a lock state where said PLL is unlocked.
Claim 21
Dependent Claim
38 words
The clock circuit of claim 17 further including: a synchronizing circuit configured to synchronize said lock signal relative to said input clock signal to generate a synchronized lock signal wherein said synchronized lock signal defines said control signal.
Claim 22
Dependent Claim
43 words
The clock circuit of claim 18 wherein said lock detector generates said lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal.
Claim 23
Dependent Claim
30 words
The clock circuit of claim 18 wherein said logic gate comprises an AND gate having a pair of input terminals for receiving said control signal and said input clock signal.
Claim 24
Dependent Claim
49 words
The clock circuit of claim 18 wherein said synchronizing circuit includes a D-type flip flop having a data input terminal for receiving said lock signal, an clock terminal for receiving said input clock signal, and a data output terminal for outputting said synchronized lock signal defining said control signal.
Claim 25
Dependent Claim
109 words
The clock circuit of claim 18 wherein said lock detector generates said lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal, said logic gate comprises an AND gate having a pair of input terminals for receiving said control signal and said input clock signal, and said synchronizing circuit includes a D-type flip flop having a data input terminal for receiving said lock signal, an clock terminal for receiving said input clock signal, and a data output terminal for outputting said synchronized lock signal defining said control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |