US5311602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for compressing digital images while retaining image fidelity
Assignee: Unisys Corp
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Filing: 1992-02-25
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Granted: 1994-05-10
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Expires: 2012-02-25
Abstract
Abstract An image compressing circuit is comprised of: a number generating circuit which generates a respective number for each X-bit pixel in an input image such that the respective number changes in a cyclic fashion from pixel to pixel across each row of pixels in the input image; and, a translator circuit which performs a translation on each individual X-bit pixel together with its respective number to produce a corresponding Y-bit pixel, where Y is less than X. This translation is one which, when performed sequentially on several consecutive X-bit pixels of a single magnitude and their respective numbers for one cycle of the numbers, produces a series of Y-bit pixels of one or two magnitudes with an average value that increases monotonically as the single magnitude increases. By these Y-bit pixel series, the fidelity of the input image is retained even though Y is less then X.
Inventors
- 👤 Donald J. Nieglos
- 👤 Daniel A. Neuss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:19
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/40087
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
192 words
An image compressing circuit which is comprised of: a video input circuit for producing first electrical input signals which represent a digital input image that is made of multiple rows of X-bit pixels; a number generating circuit, coupled to said video input circuit, which generates second electrical input signals that identify a respective number for each X-bit pixel in said input image such that across each row the numbers occur as a particular number series which cyclically repeats; a translator circuit, coupled to said video input circuit and number generating circuit, which performs a translation on each individual X-bit pixel together with its respective number to produce an electrical output signal that represents a corresponding Y-bit pixel, where Y is less than X and more than one; and, said translation, when performed sequentially on consecutive X-bit pixels of a single magnitude in a row for two cycles of said numbers, producing two identical series of said Y-bit pixels with a) all of said Y-bit pixels within a series having only one or two magnitudes and b) said Y-bit pixel series having an average value that increases monotonically as said single magnitude increases.
Claim 2
Dependent Claim
192 words
An image compressing circuit which is comprised of: a video input circuit for producing first electrical input signals which represent a digital input image that is made of multiple rows of X-bit pixels; a number generating circuit, coupled to said video input circuit, which generates second electrical input signals that identify a respective number for each X-bit pixel in said input image such that across each row the numbers occur as a particular number series which cyclically repeats; a translator circuit, coupled to said video input circuit and number generating circuit, which performs a translation on each individual X-bit pixel together with its respective number to produce an electrical output signal that represents a corresponding Y-bit pixel, where Y is less than X and more than one; and, said translation, when performed sequentially on consecutive X-bit pixels of a single magnitude in a row for two cycles of said numbers, producing two identical series of said Y-bit pixels with a) all of said Y-bit pixels within a series having only one or two magnitudes and b) said Y-bit pixel series having an average value that increases monotonically as said single magnitude increases.
Claim 3
Dependent Claim
40 words
An image compressing circuit according to claim 1 wherein said translator circuit includes a memory which has said Y-bit pixels stored therein and which is addressed by said individual X-bit pixel together with its respective number to perform said translation.
Claim 4
Dependent Claim
30 words
An image compressing circuit according to claim 1 wherein said translator circuit includes a logic circuit which logically combines each X-bit pixel and its respective number to perform said translation.
Claim 5
Dependent Claim
52 words
An image compressing circuit according to claim 1 wherein said translator circuit generates said Y-bit pixel as the integer part of F 1 P i +F 2 N i where P i is said X-bit pixel, N i is said respective number, and F 1 is 6/32 and F 2 is 1/4.
Claim 6
Dependent Claim
34 words
An image compressing circuit according to claim 1 wherein said translator circuit produces a total of (2 Y )(N)-(N-1) different Y-bit pixel series, where N is the total number of respective numbers per cycle.
Claim 7
Dependent Claim
25 words
An image compressing circuit according to claim 1 wherein one complete cycle of respective numbers from said number generating circuit is less than nine numbers.
Claim 8
Dependent Claim
46 words
An image compressing circuit according to claim 1 wherein said number generator generates said respective number in one particular cyclic sequence for alternate rows of said X-bit pixels, and generates said respective number in a different cyclic sequence for all remaining rows of said X-bit pixels.
Claim 9
Dependent Claim
18 words
An image compressing circuit according to claim 1 wherein said number generating circuit is a cyclic digital counter.
Claim 10
Dependent Claim
47 words
An image compressing circuit according to claim 1 wherein associated with each of said X-bit pixels in said digital input image are two other X-bit pixels, and wherein said translator circuit translates all three associated X-bit pixels using the same number for each of the three translations.
Claim 11
Dependent Claim
40 words
An image compressing circuit according to claim 6 wherein said translator circuit includes a memory which has said Y-bit pixels stored therein and which is addressed by said individual X-bit pixel together with its respective number to perform said translation.
Claim 12
Dependent Claim
40 words
An image compressing circuit according to claim 7 wherein said translator circuit includes a memory which has said Y-bit pixels stored therein and which is addressed by said individual X-bit pixel together with its respective number to perform said translation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |