Time base correction apparatus

Claim 1

An apparatus for compensating for a time base error of a video signal, in which an input video signal sampled by a first clock signal corresponding with a time base error of the input video signal is stored in memory means and read out therefrom by a second clock signal having a fixed frequency, the apparatus comprising: signal generation means for generating a master clock signal having a constant frequency; signal output means for detecting a difference between a standard and an interval of a synchronizing signal of the input video signal of the basis of the master clock signal, to output a difference signal indicating the difference; control means responsive to the difference signal for controlling a phase of an intermediate signal on the basis of the master clock signal, thus to output the first clock signal; sampling means for sampling the input video signal by the first clock signal; and clock generating means for generating the second clock signal derived from the master clock signal; wherein, the signal output means comprises: a counter for down-counting from a predetermined number by the master clock signal in the interval of the synchronizing signal included in the input video signal, to output a pulse signal according to a difference between a counted number of the master clock signal and the predetermined number; and a comparator for comparing the predetermined number and the number of the master clock signal counted during the interval of the synchronizing signal, to output a positive signal when the predetermined number is smaller than the counted number, and to output a negative signal when the predetermined number is larger than the counted number.

Claim 2

An apparatus for compensating for a time base error of a video signal, in which an input video signal sampled by a first clock signal corresponding with a time base error of the input video signal is stored in memory means and read out therefrom by a second clock signal having a fixed frequency, the apparatus comprising: signal generation means for generating a master clock signal having a constant frequency; signal output means for detecting a difference between a standard and an interval of a synchronizing signal of the input video signal of the basis of the master clock signal, to output a difference signal indicating the difference; control means responsive to the difference signal for controlling a phase of an intermediate signal on the basis of the master clock signal, thus to output the first clock signal; sampling means for sampling the input video signal by the first clock signal; and clock generating means for generating the second clock signal derived from the master clock signal; wherein, the signal output means comprises: a counter for down-counting from a predetermined number by the master clock signal in the interval of the synchronizing signal included in the input video signal, to output a pulse signal according to a difference between a counted number of the master clock signal and the predetermined number; and a comparator for comparing the predetermined number and the number of the master clock signal counted during the interval of the synchronizing signal, to output a positive signal when the predetermined number is smaller than the counted number, and to output a negative signal when the predetermined number is larger than the counted number.

Claim 4

An apparatus for compensating for a time base error of a video signal, in which an input video signal sampled by a first clock signal corresponding with a time base error of the input video signal is stored in memory means and read out therefrom by a second clock signal having a fixed frequency, comprising: signal generation means for generating a master clock signal having a constant frequency; signal output means for detecting a difference between a standard and an interval of a synchronizing signal of the input video signal of the basis of the master clock signal, to output a difference signal indicating the difference, said signal output means comprising: a counter for down-counting from a predetermined number by the master clock signal in the interval of the synchronizing signal included in the input video signal, to output a pulse signal according to a difference between a counted number of the master clock signal and the predetermined number; and a comparator for comparing the predetermined number and the number of the master clock signal counted during the interval of the synchronizing signal, to output a positive signal when the predetermined number is smaller than the counted number, and to output a negative signal when the predetermined number is larger than the counted number; control means responsive to the difference signal for controlling a phase of an intermediate signal on the basis of the master clock signal, thus to output the first clock signal; sampling means for sampling the input video signal by the first clock signal; clock generating means for generating the second clock signal derived from the master clock signal; the control means comprises second signal generation means for generating the intermediate signal containing a specific number of pulse trains obtained from frequency division of the master clock signal and having the same phase difference; selection means for selecting a pulse train from the intermediate signal having a phase closest to a phase of the synchronizing signal included in the input video signal, and responsive to the positive or negative signal and a pulse of the pulse signal for changing the selected pulse train from the intermediate signal, to output the first clock signal.

Claim 5

An apparatus for compensating for a time base error of a video signal, in which an input video signal sampled by a first clock signal corresponding with a time base error of the input video signal is stored in memory means and read out therefrom by a second clock signal having a fixed frequency, comprising: signal generation means for generating a master clock signal having a constant frequency; signal output means for detecting a difference between a standard and an interval of a synchronizing signal of the input video signal of the basis of the master clock signal, to output a difference signal indicating the difference, said signal output means comprising: a counter for down-counting from a predetermined number by the master clock signal in the interval of the synchronizing signal included in the input video signal, to output a pulse signal according to a difference between a counted number of the master clock signal and the predetermined number; and a comparator for comparing the predetermined number and the number of the master clock signal counted during the interval of the synchronizing signal, to output a positive signal when the predetermined number is smaller than the counted number, and to output a negative signal when the predetermined number is larger than the counted number; control means responsive to the difference signal for controlling a phase of an intermediate signal on the basis of the master clock signal, thus to output the first clock signal; sampling means for sampling the input video signal by the first clock signal; clock generating means for generating the second clock signal derived from the master clock signal; the control means comprises second signal generation means for generating the intermediate signal containing a specific number of pulse trains obtained from frequency division of the master clock signal and having the same phase difference; selection means for selecting a pulse train from the intermediate signal having a phase closest to a phase of the synchronizing signal included in the input video signal, and responsive to the positive or negative signal and a pulse of the pulse signal for changing the selected pulse train from the intermediate signal, to output the first clock signal.