Time base corrector

Claim 2

A time base corrector according to Claim 1, wherein said interpolation filter comprises: delay means having cascade connection of a plurality of delay circuits for obtaining a plurality of sample values by delaying an input signal of said interpolation means; selectors for selecting a predetermined number of sample values from said plurality of delay circuits based on time base error information from the time base error detector; a plurality of multipliers for multiplying a predetermined number of sample values selected by said selectors with coefficients based on time base error information from said time base error detector; and an adder for adding outputs from said plurality of multipliers to obtain an interpolation output from said interpolation filter.

Claim 3

A time base corrector according to Claim 1, wherein said time base error detector has a time base error calculating circuit for obtaining and outputting a time base error smaller than one sampling time in a digital signal by an arithmetic operation, and outputs time base errors to be corrected for each horizontal scanning time by using an output from said time base error calculating circuit.

Claim 4

A time base corrector according to Claim 1, wherein said time base error detector comprises: a time base error calculating circuit for obtaining and outputting a time base error smaller than one sampling time in a digital signal by an arithmetic operation; and a velocity error detector for obtaining an error from one reference horizontal scanning time by using an output from said time base error calculating circuit; and produces output time base errors to be corrected for each one sampling time by using an output from said time base error calculating circuit and an output from said velocity error detector.

Claim 5

A time base corrector comprising: first, second and third A/D converters for sampling total three input signals of a video luminance signal and two color differential signals of a signal U and a signal V, by a clock signal having a predetermined time interval respectively and for converting these signals into digital signals; a first multiplexor for multiplexing a signal U and a signal V converted into digital signals, on a time base; a first memory for temporarily storing a digital luminance signal obtained by said first A/D converter; a second memory for temporarily storing an output from said first multiplex circuit; a write address generator for resetting write addresses of said first and second memories each time when a horizontal synchronizing signal in a digital signal obtained by said first A/D converter has been detected; a second multiplexor for multiplexing outputs from said first and second memories on a time base; a time base error detector for detecting a time base error of the digital signal obtained by said first A/D converter and for outputting time base error information to be used at the time of interpolating based on the detected error; an interpolation filter for obtaining a digital signal having a reference time base by interpolating a signal amplitude in the form of a multiplex signal based on time base error information from a digital signal produced from said second multiplex circuit; a separator for separating an original time base signal from a time-base multiplexed digital signal produced from said interpolation filter; and first, second and third D/A converters for converting three output signals of said separator into analog signals in the same time interval as that of the clock signal used in said A/D converter.

Claim 6

A time base corrector according to Claim 5, wherein said interpolation filter comprises: delay means including a plurality of delay circuits for delaying a time-base multiplexed input signal to this interpolation filter to obtain a plurality of continuous sample values before the multiplexing; selectors for selecting and outputting a predetermined number of sample values from said plurality of sample values based on time base error information from the time base error detector and data structure; a plurality of multipliers for multiplying a predetermined number of sample values selected by said selectors with coefficients based on time base error information from said time base error detector respectively; and an adder for adding outputs from said plurality of multipliers to obtain an interpolation output of said interpolation filter.

Claim 7

A time base corrector according to Claim 5, wherein a sampling frequency to be used for converting an input signal into a digital signal by said second and third A/D converters is a frequency of one fourth of the sampling frequency used in said first A/D converter.

Claim 8

A time base corrector according to Claim 5, wherein the phase of the clock signal to be used at the time of converting an input signal into a digital signal by said second and third A/D converters is set such that the phase to be used by said second A/D converter and the phase to be used by said third A/D converter are differentiated by 180 degrees between them.