Patent US6318911B1 successfully refreshed from Google Patents.
US6318911B1
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Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program
Assignee: Toshiba Corp
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Filing: 1998-03-31
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Granted: 2001-11-20
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Expires: 2018-03-31
Abstract
Abstract Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.
Inventors
- 👤 Takeshi Kitahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:57
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
121 words
A gated clock design supporting method comprising the steps of: inputting information about a logic circuit not a clock-gated, information about enable logic for controlling clock output and information about a gating circuit; generating a timing constraint to be secured for said enable logic; calculating a delay time in said enable logic; determining whether or not said enable logic satisfies said timing constraint based on said delay time; when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 2
Dependent Claim
121 words
A gated clock design supporting method comprising the steps of: inputting information about a logic circuit not a clock-gated, information about enable logic for controlling clock output and information about a gating circuit; generating a timing constraint to be secured for said enable logic; calculating a delay time in said enable logic; determining whether or not said enable logic satisfies said timing constraint based on said delay time; when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 3
Dependent Claim
27 words
A gated clock design supporting method according to claim 1 , wherein said gating circuit includes a circuit for securing a normal operation for the logic circuit.
Claim 4
Dependent Claim
29 words
A gated clock design supporting method according to claim 1 , further comprising the step of: generating information about a gate a clock line of said clock-gated logic circuit.
Claim 5
Dependent Claim
51 words
A gated clock design supporting method according to claim 1 , further comprising the step of outputting, when said enable logic does not satisfy the timing constraint, an error message indicating that a timing constraint error has occurred relating to an enable logic portion which does not satisfy said timing constraint.
Claim 6
Dependent Claim
35 words
A gated clock design supporting method according to claim 1 , wherein information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic are displayed on a display unit.
Claim 7
Dependent Claim
42 words
A gated clock design supporting method according to claim 1 , wherein information about said logic circuit not clock-gated, information about said enable logic and information about said gating circuit are inputted in the form of text information through a key board.
Claim 8
Dependent Claim
30 words
A gated clock design supporting method according to claim 1 , wherein information about said logic circuit not clock-gated is inputted by drawing on a screen of a display unit.
Claim 9
Dependent Claim
152 words
A gated clock design supporting apparatus comprising: a circuit information input portion for inputting information about a logic circuit not clock-gated, information about enable logic for controlling a clock output and information about a gating circuit; an enable logic timing constraint generating portion for generating a timing constraint to be secured for said enable logic; an enable logic timing determination portion for calculating a delay time in said enable logic and determining whether or not said enable logic satisfies said timing constraint based on said delay time; a clock gating execution portion for, when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and a circuit information output portion for outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 10
Dependent Claim
152 words
A gated clock design supporting apparatus comprising: a circuit information input portion for inputting information about a logic circuit not clock-gated, information about enable logic for controlling a clock output and information about a gating circuit; an enable logic timing constraint generating portion for generating a timing constraint to be secured for said enable logic; an enable logic timing determination portion for calculating a delay time in said enable logic and determining whether or not said enable logic satisfies said timing constraint based on said delay time; a clock gating execution portion for, when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and a circuit information output portion for outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 11
Dependent Claim
27 words
A gated clock design supporting apparatus according to claim 8 , wherein said gating circuit includes a circuit for securing a normal operation for the logic circuit.
Claim 12
Dependent Claim
35 words
A gated clock design supporting apparatus according to claim 8 , further comprising: a clock line gate information generating portion for generating information about a gate on a clock line of said clock-gated logic circuit.
Claim 13
Dependent Claim
60 words
A gated clock design supporting apparatus according to claim 8 , wherein when said enable logic timing determination portion determines that said enable logic does not satisfy the timing constraint, said circuit information output portion outputs an error message indicating that a timing constraint error has occurred relating to an enable logic portion which does not satisfy said timing constraint.
Claim 14
Dependent Claim
21 words
A gated clock design supporting apparatus according to claim 8 , wherein said circuit information input portion comprises a key board.
Claim 15
Dependent Claim
40 words
A gated clock design supporting apparatus according to claim 8 , wherein said circuit information input portion comprises a display unit and information about said logic circuit not clock-gated is inputted by drawing on a screen of said display unit.
Claim 16
Dependent Claim
130 words
A computer-readable memory storing gated clock design supporting program, said gated clock design supporting program comprising the steps of: inputting information about a logic circuit not clock-gated, information about enable logic for controlling a clock output and information about a gating circuit; generating a timing constraint to be secured for said enable logic; calculating a delay time in said enable logic; determining whether or not said enable logic satisfies said timing constraint based on said delay time; when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 17
Dependent Claim
130 words
A computer-readable memory storing gated clock design supporting program, said gated clock design supporting program comprising the steps of: inputting information about a logic circuit not clock-gated, information about enable logic for controlling a clock output and information about a gating circuit; generating a timing constraint to be secured for said enable logic; calculating a delay time in said enable logic; determining whether or not said enable logic satisfies said timing constraint based on said delay time; when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.
Claim 18
Dependent Claim
30 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , wherein said gating circuit includes a circuit for securing a normal operation for the logic circuit.
Claim 19
Dependent Claim
33 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , further comprising the step of: generating information about a gate on a clock line of said clock-gated logic circuit.
Claim 20
Dependent Claim
59 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , further comprising the step of: when said determining step determines that said enable logic does not satisfy the timing constraint, outputting an error message indicating that a timing constraint error has occurred relating to an enable logic portion which does not satisfy said timing constraint.
Claim 21
Dependent Claim
42 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , wherein at said outputting step, information about said logic circuit clock-gated and said timing constraint to be secured for said enable logic are displayed on a display unit.
Claim 22
Dependent Claim
49 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , where at said inputting step, information about said logic circuit not clock-gated, information about said enable logic and information about said gating circuit are inputted in the form of text information through a key board.
Claim 23
Dependent Claim
37 words
A computer-readable memory storing gated clock design supporting program according to claim 14 , where at said inputting step, information about said logic circuit not clock-gated is inputted by drawing on a screen of a display unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-19 | 2005-05-21 | 2005-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-19 | 2009-05-21 | 2009-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-19 | 2013-05-21 | 2013-11-20 | $7700.00 | Window Closed / Lapsed |