US5825658A
Expired / Lapsed
US
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Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit
Assignee: NXP BV
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Filing: 1995-09-14
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Granted: 1998-10-20
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Expires: 2015-09-14
Abstract
Abstract In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable. The computer aided design system then automatically verifies that the integrated circuit satisifies the specified timing constraints. During the timing constraint verification process, for mutli-clock timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated only through signal paths consistent with the constraint based timing path specifications. In addition, the verified netlist, timing constraints and constraint based timing path specifications may be passed to a silicon compiler for automatically placing/routing a circuit in accordance with the netlist, timing constraints and constraint based timing path specifications.
Inventors
- 👤 Arnold Ginetti
- 👤 Athanasius W. Spyrou
- 👤 Jean-Michel Fernandez
- 👤 Francois Silve
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:19
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
252 words
A method of specifying and analyzing multiple timing constraints in an integrated circuit, the steps of the method comprising: (A) receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (B) receiving and storing in said computer memory a plurality of system level timing constraints, said system level timing constraints representing maximum delay times for signals to propagate from input nodes to output nodes of said integrated circuit; (C) receiving and storing in said computer memory data at least one clock timing constraint and a plurality multi-cycle timing constraints, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (D) receiving and storing in said computer memory a plurality of constraint based timing path specifications, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; and (E) verifying satisfaction of said timing constraints by said integrated circuit.
Claim 2
Independent Claim
252 words
A method of specifying and analyzing multiple timing constraints in an integrated circuit, the steps of the method comprising: (A) receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (B) receiving and storing in said computer memory a plurality of system level timing constraints, said system level timing constraints representing maximum delay times for signals to propagate from input nodes to output nodes of said integrated circuit; (C) receiving and storing in said computer memory data at least one clock timing constraint and a plurality multi-cycle timing constraints, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (D) receiving and storing in said computer memory a plurality of constraint based timing path specifications, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; and (E) verifying satisfaction of said timing constraints by said integrated circuit.
Claim 3
Dependent Claim
69 words
The method of claim 1 wherein said verifying step includes the steps of: propagating signal arrival times at each of said plurality of interconnected components; and back-propagating required signal arrival times at each of said plurality of interconnected components; wherein for multi-cycle timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated only through signal paths consistent with said stored constraint based timing path specifications.
Claim 4
Dependent Claim
41 words
The method of claim 1, further including: (G) passing said netlist, timing constraints and constraint based timing path specifications to a silicon compiler and automatically placing/routing a circuit in accordance with said netlist, timing constraints and constraint based timing path specifications.
Claim 5
Dependent Claim
284 words
A computer aided circuit design system for synthesizing an integrated circuit, comprising: (A) a computer memory; (B) a netlist stored in said computer memory, said netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (C) a plurality of system level timing constraints stored in said computer memory, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit; (D) at least one clock timing constraint and a plurality multi-cycle timing constraints, stored in said computer memory, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (E) a plurality of constraint based timing path specifications stored in said memory, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; (F) cell delay data stored in said computer memory, said cell delay data representing signal delays associated with said components in said integrated circuit; and (G) a timing verifier for automatically determining whether an integrated circuit designed in accordance with said netlist would satisfy said timing constraints.
Claim 6
Dependent Claim
284 words
A computer aided circuit design system for synthesizing an integrated circuit, comprising: (A) a computer memory; (B) a netlist stored in said computer memory, said netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (C) a plurality of system level timing constraints stored in said computer memory, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit; (D) at least one clock timing constraint and a plurality multi-cycle timing constraints, stored in said computer memory, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (E) a plurality of constraint based timing path specifications stored in said memory, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; (F) cell delay data stored in said computer memory, said cell delay data representing signal delays associated with said components in said integrated circuit; and (G) a timing verifier for automatically determining whether an integrated circuit designed in accordance with said netlist would satisfy said timing constraints.
Claim 7
Dependent Claim
69 words
The system of claim 4 wherein said timing verifier: propagates signal arrival times at each of said plurality of interconnected components; and back-propagates required signal arrival times at each of said plurality of interconnected components; wherein for multi-cycle timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated by said timing verifier only through signal paths consistent with said stored constraint based timing path specifications.
Claim 8
Dependent Claim
30 words
The system of claim 4, further including: (H) a silicon compiler for automatically placing/routing an integrated circuit in according with said netlist, timing constraints and constraint based timing path specifications.
Claim 9
Dependent Claim
285 words
A computer aided circuit design system for synthesizing an integrated circuit, comprising: (A) a computer memory; (B) a netlist stored in said computer memory, said netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (C) a plurality of system level timing constraints stored in said computer memory, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit; (D) at least one clock timing constraint and a plurality multi-cycle timing constraints, stored in said computer memory, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (E) a plurality of constraint based timing path specifications stored in said memory, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; (F) cell delay data stored in said computer memory, said cell delay data representing signal delays associated with said components in said integrated circuit; and (G) a silicon compiler for automatically placing/routing an integrated circuit in according with said netlist, timing constraints and constraint based timing path specifications.
Claim 10
Dependent Claim
285 words
A computer aided circuit design system for synthesizing an integrated circuit, comprising: (A) a computer memory; (B) a netlist stored in said computer memory, said netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; (C) a plurality of system level timing constraints stored in said computer memory, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit; (D) at least one clock timing constraint and a plurality multi-cycle timing constraints, stored in said computer memory, said clock timing constraint and said multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of said clock based timing constraints concern timing constraints for duration longer than a single clock period; (E) a plurality of constraint based timing path specifications stored in said memory, each indicating signal paths through said integrated circuit to which specified ones of said multi-cycle timing constraints are applicable and signal paths to which said specified ones of said multi-cycle timing constraints are not applicable; (F) cell delay data stored in said computer memory, said cell delay data representing signal delays associated with said components in said integrated circuit; and (G) a silicon compiler for automatically placing/routing an integrated circuit in according with said netlist, timing constraints and constraint based timing path specifications.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |