Patent US6314052B2 successfully refreshed from Google Patents.
US6314052B2
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Delayed locked loop implementation in a synchronous dynamic random access memory
Assignee: Mosaid Technologies Inc
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Filing: 2001-01-16
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Granted: 2001-11-06
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Expires: 2021-01-16
Abstract
Abstract A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Inventors
- 👤 Richard C. Foss
- 👤 Peter B. Gillingham
- 👤 Graham Allan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:35
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/00; G11C7/10; G11C7/1051; G11C7/1072; G11C7/22; G11C7/222; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/0814
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
182 words
A clock applying circuit for a synchronous memory comprising: (a) a clock input for receiving a clock input signal; (b) means connected to the synchronous memory for receiving a driving clock signal; (c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal; (d) means for providing the driving clock signal from an output of one of the delay elements; (e) means for selecting an output from said one of the delay elements comprising a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory; and (f) means for providing the driving clock signal to said particular enable terminal.
Claim 2
Dependent Claim
182 words
A clock applying circuit for a synchronous memory comprising: (a) a clock input for receiving a clock input signal; (b) means connected to the synchronous memory for receiving a driving clock signal; (c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal; (d) means for providing the driving clock signal from an output of one of the delay elements; (e) means for selecting an output from said one of the delay elements comprising a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory; and (f) means for providing the driving clock signal to said particular enable terminal.
Claim 3
Dependent Claim
66 words
A clock applying circuit as defined in claim 1 including delay model means having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, an input port of the delay model means for receiving the driving clock signal and for providing a delayed driving signal to the comparator.
Claim 4
Dependent Claim
66 words
A clock applying circuit as defined in claim 2 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof, means for receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
Claim 5
Dependent Claim
47 words
A clock applying circuit as defined in claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof and for outputting one of the output signals as the driving clock signal.
Claim 6
Dependent Claim
66 words
A clock applying circuit as defined in claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof, means for receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
Claim 7
Dependent Claim
63 words
A clock applying circuit as defined in claim 1 including a delay model having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, an input port of the delay model receiving the driving clock signal and providing a delayed driving signal to the comparator.
Claim 8
Dependent Claim
63 words
A clock applying circuit as defined in claim 6 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof, and receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
Claim 9
Dependent Claim
141 words
A clock applying circuit for a synchronous memory comprising: a clock input receiving a clock input signal; a tapped delay line receiving the clock input signal and delivering a clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal; and a selector selecting an output from said one of the delay elements to provide the driving clock signal, the selector comprising a comparator comparing the clock input signal with said driving clock signal and the selector selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory.
Claim 10
Dependent Claim
141 words
A clock applying circuit for a synchronous memory comprising: a clock input receiving a clock input signal; a tapped delay line receiving the clock input signal and delivering a clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal; and a selector selecting an output from said one of the delay elements to provide the driving clock signal, the selector comprising a comparator comparing the clock input signal with said driving clock signal and the selector selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory.
Claim 11
Dependent Claim
45 words
A clock applying circuit as defined in claim 8 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof and for outputting one of the output signals as the driving clock signal.
Claim 12
Dependent Claim
63 words
A clock applying circuit as defined in claim 8 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof, and receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-05 | 2005-05-07 | 2005-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-05 | 2009-05-07 | 2009-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-05 | 2013-05-07 | 2013-11-06 | $7700.00 | Window Closed / Lapsed |