Fabrication method for an electrically erasable programmable read only memory

Claim 1

A method for fabricating an electrically erasable programmable read only memory, comprising: providing a substrate having at least a strip of a active area formed thereon, and two isolation structures on the two sides of the active area formed therein; forming an oxide layer on the substrate; forming a trench in the oxide layer to expose the substrate area designated for a source, the trench being perpendicular to the active area; filling the trench with a polysilicon layer to form a polysilicon pillar; implanting ions into the polysilicon pillar and the substrate area designated for the source; performing an annealing process to drive the ions into the substrate area designated for the source; removing the oxide layer; forming a first dielectric layer to cover the polysilicon pillar and the substrate; depositing a first doped polysilicon layer on the substrate; patterning the first doped polysilicon layer to form two floating gates in parallel with the polysilicon pillar, the two floating gates covering the sidewall and the top portion of the polysilicon pillar, respectively; removing the exposed first dielectric layer; forming a second dielectric layer on the substrate; forming a conformal second dielectric layer covering the two floating gates and the substrate; forming a second doped polysilicon layer on the substrate and patterning the second doped polysilicon layer into two control gates in parallel with the polysilicon pillar, the two control gates covering the sidewall and the top portion of the two floating gates; and implanting ions into the substrate area designated for two drains using the control gates as a mask.

Claim 2

A method for fabricating an electrically erasable programmable read only memory, comprising: providing a substrate having at least a strip of a active area formed thereon, and two isolation structures on the two sides of the active area formed therein; forming an oxide layer on the substrate; forming a trench in the oxide layer to expose the substrate area designated for a source, the trench being perpendicular to the active area; filling the trench with a polysilicon layer to form a polysilicon pillar; implanting ions into the polysilicon pillar and the substrate area designated for the source; performing an annealing process to drive the ions into the substrate area designated for the source; removing the oxide layer; forming a first dielectric layer to cover the polysilicon pillar and the substrate; depositing a first doped polysilicon layer on the substrate; patterning the first doped polysilicon layer to form two floating gates in parallel with the polysilicon pillar, the two floating gates covering the sidewall and the top portion of the polysilicon pillar, respectively; removing the exposed first dielectric layer; forming a second dielectric layer on the substrate; forming a conformal second dielectric layer covering the two floating gates and the substrate; forming a second doped polysilicon layer on the substrate and patterning the second doped polysilicon layer into two control gates in parallel with the polysilicon pillar, the two control gates covering the sidewall and the top portion of the two floating gates; and implanting ions into the substrate area designated for two drains using the control gates as a mask.

Claim 6

A method for fabricating a stacked source structure, wherein the stacked source structure is for a flash memory, the steps of the method comprising providing a substrate; forming a doped polysilicon pillar on the substrate; forming a polymer layer on the doped polysilicon pillar and the substrate and then baking the polymer layer to solidify the polymer layer; removing the polymer layer by a dry etching step until upper comers of the doped polysilicon pillar are exposed; removing the upper comers of the doped polysilicon pillar to form a doped polysilicon pillar with modified comers; and forming a source in the substrate beneath the doped polysilicon pillar, wherein an annealing process is performed to drive dopants in the doped polysilicon pillar into the substrate to form the source.

Claim 7

A method for fabricating a stacked source structure, wherein the stacked source structure is for a flash memory, the steps of the method comprising providing a substrate; forming a doped polysilicon pillar on the substrate; forming a polymer layer on the doped polysilicon pillar and the substrate and then baking the polymer layer to solidify the polymer layer; removing the polymer layer by a dry etching step until upper comers of the doped polysilicon pillar are exposed; removing the upper comers of the doped polysilicon pillar to form a doped polysilicon pillar with modified comers; and forming a source in the substrate beneath the doped polysilicon pillar, wherein an annealing process is performed to drive dopants in the doped polysilicon pillar into the substrate to form the source.

Claim 8

A method for fabricating a stacked source structure, wherein the stacked source structure is for a flash memory, the steps of the method comprising providing a substrate; forming a doped polysilicon pillar on the substrate; forming a source in the substrate beneath the doped polysilicon pillar, wherein an annealing process is performed to drive dopants in the doped polysilicon pillar into the substrate to form the source; forming a first dielectric layer to cover the doped polysilicon pillar and the substrate; forming a first doped polysilicon layer on the first dielectric layer; forming a photoresist layer on the first doped polysilicon layer, wherein the photoresist layer is not solidified as coated, and a thickness of a portion of the photoresist layer on top of the first doped polysilicon is thinner than thicknesses of other portions of the photoresist layer; blanket etching the photoresist layer to cut the photoresist layer on top of the doped polysilicon pillar and to expose the first doped polysilicon layer; and etching the first doped polysilicon layer using the photoresist layer with a cut as a mask to cut the first doped polysilicon layer, thereby forming two floating gates covering the sidewall and the top portion of the doped polysilicon pillar.

Claim 9

A method for fabricating a stacked source structure, wherein the stacked source structure is for a flash memory, the steps of the method comprising providing a substrate; forming a doped polysilicon pillar on the substrate; forming a source in the substrate beneath the doped polysilicon pillar, wherein an annealing process is performed to drive dopants in the doped polysilicon pillar into the substrate to form the source; forming a first dielectric layer to cover the doped polysilicon pillar and the substrate; forming a first doped polysilicon layer on the first dielectric layer; forming a photoresist layer on the first doped polysilicon layer, wherein the photoresist layer is not solidified as coated, and a thickness of a portion of the photoresist layer on top of the first doped polysilicon is thinner than thicknesses of other portions of the photoresist layer; blanket etching the photoresist layer to cut the photoresist layer on top of the doped polysilicon pillar and to expose the first doped polysilicon layer; and etching the first doped polysilicon layer using the photoresist layer with a cut as a mask to cut the first doped polysilicon layer, thereby forming two floating gates covering the sidewall and the top portion of the doped polysilicon pillar.