US6301191B1
Expired / Lapsed
US
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Semiconductor memory device allowing reduction in power consumption during standby
Assignee: Renesas Electronics Corp
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Filing: 2000-11-28
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Granted: 2001-10-09
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Expires: 2020-11-28
Abstract
Abstract A synchronous signal generating circuit 100 includes a delay circuit 110 which receives and delays an external clock signal Ext.CLK by a predetermined time for issuing the same, a phase comparator 120 which compares an output of the delay circuit 110 with a phase of the external clock signal Ext.CLK, a variable constant current source circuit 140 which varies in a digital manner a value of a constant current supplied to an output node 140a based on a result of comparison by the phase comparator 120, and a delay control circuit 150 which adjusts a degree of delay by the delay circuit 110 in accordance with the value of the constant current supplied to the output node 140a. The degree of delay by the delay circuit 110 is controlled in accordance with the value of the constant current which varies linearly in accordance with the result of phase comparison.
Inventors
- 👤 Tsukasa Ooishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:18
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/089; H03L7/0891; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
A synchronous semiconductor memory device operable in synchronization with an external clock signal comprising: an internal synchronizing circuit for suspending a synchronizing operation to generate an internal clock signal synchronized with said external clock signal before activation transition of a memory activation signal and beginning said synchronizing operation in response to the activation transition of said memory activation signal; a plurality of memory cells, arranged in a matrix form, for storing storage data respectively; and a memory cell access circuit for beginning to select a memory cell independently of said internal clock signal upon activation of said memory activation signal, and writing/reading said storage data to/from the selected memory cell according to said internal clock signal synchronized with said external clock signal.
Claim 2
Dependent Claim
122 words
A synchronous semiconductor memory device operable in synchronization with an external clock signal comprising: an internal synchronizing circuit for suspending a synchronizing operation to generate an internal clock signal synchronized with said external clock signal before activation transition of a memory activation signal and beginning said synchronizing operation in response to the activation transition of said memory activation signal; a plurality of memory cells, arranged in a matrix form, for storing storage data respectively; and a memory cell access circuit for beginning to select a memory cell independently of said internal clock signal upon activation of said memory activation signal, and writing/reading said storage data to/from the selected memory cell according to said internal clock signal synchronized with said external clock signal.
Claim 3
Dependent Claim
52 words
The synchronous semiconductor memory device according to claim 1 , wherein said memory cell access circuit includes a column select circuit, in synchronization with said internal clock signal, for selecting a column of said memory cells in accordance with a column address signal and writing/reading said storage data to/from the selected column.
Claim 4
Dependent Claim
94 words
The synchronous semiconductor memory device according to claim 1 , wherein said memory activation signal is a row operation activation signal, and said memory cell access circuit includes a row select circuit, activated in response to activation of said row operation activation signal, for selecting a row of said memory cells in accordance with a row address signal; and a column select circuit for selecting a column of said memory cells in accordance with a column address signal, and writing/reading said storage data to/from the selected column in synchronization with said internal clock signal.
Claim 5
Dependent Claim
28 words
The synchronous semiconductor memory device according to claim 1 , wherein said internal synchronizing circuit suspends said synchronizing operation in response to inactivation of said memory activation signal.
Claim 6
Dependent Claim
111 words
The synchronous semiconductor memory device according to claim 1 , wherein said internal synchronizing circuit includes a phase comparator for beginning to compare a phase of said external clock signal with a phase of said internal clock signal in response to the activation transition of said memory activation signal, an internal clock generator for generating said internal clock signal having a phase associated with a control signal, and a control circuit for digitally changing a level of said control signal by a unit amount in accordance with comparison result of said phase comparator, wherein said control circuit decreases said unit amount stepwise after the activation transition of said memory activation signal.
Claim 7
Dependent Claim
76 words
The synchronous semiconductor memory device according to claim 5 , wherein said control circuit includes a first level controller for changing the level of said control signal by a first amount to adjust the phase of said internal clock signal to the phase of said external clock signal, and a second level controller, succeeding to said first level controller, for changing the level of said control signal by a second amount smaller than the first amount.
Claim 8
Dependent Claim
71 words
The synchronous semiconductor memory device according to claim 5 , wherein said control circuit includes a plurality of sub level controllers, each of said sub level controllers having a plurality of current sources, an internal node, a switch circuit for selectively connecting said current sources to said internal node, and a converting circuit for converting an amount of current flowing to said internal node into the level of said control signal.
Claim 9
Dependent Claim
99 words
The synchronous semiconductor memory device according to claim 1 , wherein said internal synchronizing circuit includes an internal clock generator having a plurality of delay circuits, wherein said delay circuits are serially connected and delay said external clock signal by a delay time associated with a delay control signal, a determination circuit for receiving output signals from said delay circuits respectively and determining to which one of said delay circuits said external clock signal propagates, and a delay control circuit for digitally changing a level of said delay control signal in accordance with determination result of said determination circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-08 | 2005-04-09 | 2005-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-08 | 2009-04-09 | 2009-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-08 | 2013-04-09 | 2013-10-09 | $7700.00 | Window Closed / Lapsed |