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JPS6239916A Expired / Lapsed JP ⏱️ 0.0 years remaining

Pll circuit

Assignee: Akai Electric Co Ltd
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Filing: 1985-08-14
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Granted: —
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Expires: 2005-08-14
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Abstract

Abstract PURPOSE:To stably apply PLL synchronization even at a pitch control operation by providing a free run frequency changeover circuit to a control voltage input side of a voltage controlled oscillator. CONSTITUTION:A switch 8 command a prescribed pitch change externally. In turning ON the switch for 10 times, a control circuit 7 increases +10% pitch by a program. In keeping the depression, the pitch is decreased up to -10%. The control circuit 7 receiving a command of the external command switch 8 outputs a control signal 9 so as to turn ON analog electronic switches 5', 6'. A VCO2 is decided by a voltage Ve given by resistors R1, R2, R3, R4 when the free run frequency f0 sets the pitch to + or -0%. The lock range of the PLL is acted largely by the setting of the free run frequency f0. The analog electronic switch 5' is changed over so as to attain the free run frequency most suited to the pitch while using the control signal to select R5, R6...Rn thereby varying the Ve.

Inventors

  • 👤 Hideaki Furuya
  • 👤 古家 英明
  • 👤 Tetsuro Kumagai
  • 👤 熊谷 哲朗
  • 👤 Seiichi Abiru
  • 👤 安蒜 誠一
  • 👤 Shinichirou Jiyu
  • 👤 樹 伸一郎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 16:32
CPC Classifications
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Claims Analysis

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References Cited (Backward Citations)

JPS5470716A Cited
JPS5676639A Cited

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