Semiconductor device with high integration density and improved performance

Claim 1

A method for forming a semiconductor device which has a first area in which a plurality of first MOS transistors are formed and arranged with a first distance between gate electrodes in a channel length direction, and a second area in which a plurality of second MOS transistors having diffusion layers of impurity concentration higher than that of said first MOS transistors are formed and arranged with a second distance between gate electrodes longer than the first distance between the gate electrodes in the channel length direction, comprising the steps of: forming a conductive film on said first and second areas; selectively etching said conductive film on said first area to form and arrange a plurality of first gate electrodes with the first distance between said gate electrodes; selectively doping impurity into said first area between said first gate electrodes to form first diffusion layers; forming first gate side-wall insulating films on the side walls of said first gate electrodes; selectively etching said conductive film on said second area to form and arrange a plurality of second gate electrodes with the second distance between the gate electrodes; selectively doping impurity into said second area between said second gate electrodes to form second diffusion layers; forming second gate side-wall insulating films which are formed thicker than said first gate side-wall insulating films and formed of the same type of film as that of said first gate side-wall insulating films on the side walls of said second gate electrodes; and selectively doping impurity into portions of said second diffusion layers which are not covered with said second gate side-wall insulating films to form third diffusion layers.

Claim 2

A method for forming a semiconductor device which has a first area in which a plurality of first MOS transistors are formed and arranged with a first distance between gate electrodes in a channel length direction, and a second area in which a plurality of second MOS transistors having diffusion layers of impurity concentration higher than that of said first MOS transistors are formed and arranged with a second distance between gate electrodes longer than the first distance between the gate electrodes in the channel length direction, comprising the steps of: forming a conductive film on said first and second areas; selectively etching said conductive film on said first area to form and arrange a plurality of first gate electrodes with the first distance between said gate electrodes; selectively doping impurity into said first area between said first gate electrodes to form first diffusion layers; forming first gate side-wall insulating films on the side walls of said first gate electrodes; selectively etching said conductive film on said second area to form and arrange a plurality of second gate electrodes with the second distance between the gate electrodes; selectively doping impurity into said second area between said second gate electrodes to form second diffusion layers; forming second gate side-wall insulating films which are formed thicker than said first gate side-wall insulating films and formed of the same type of film as that of said first gate side-wall insulating films on the side walls of said second gate electrodes; and selectively doping impurity into portions of said second diffusion layers which are not covered with said second gate side-wall insulating films to form third diffusion layers.

Claim 5

A method for forming a semiconductor device which has a plurality of active region groups regularly arranged on the surface of a semiconductor substrate, and a plurality of wiring groups arranged in parallel to one another on and intersecting said plurality of active region groups and in which said plurality of active region groups are arranged and shifted from one another in the array direction of said plurality of wiring groups by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend and contact areas for each of said plurality of active region groups are each formed in an area extending in a projection form from each of said plurality of active region groups in a direction in which said plurality of wiring groups extend between adjacent wirings among said plurality of wiring groups, comprising the steps of: selectively covering said plurality of wiring groups with a first insulating film; filling a second insulating film in spaces between said plurality of wiring groups; forming a resist on said first and second insulating films and forming a resist pattern by exposing and developing the resist; selectively etching said second insulating film with respect to said first insulating film with said resist pattern used as a mask to form contact holes for the contact areas of said plurality of active region groups in said second insulating film; and forming a contact electrode wiring layer to fill said contact holes; wherein said resist pattern is formed by removing portions of said resist lying on said plurality of active region groups and said contact areas and on an area between the contact area of each of the active regions of said plurality of active region groups and another active region adjacent to said active region on the side of the projecting portion and shifted from said active region by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend.

Claim 6

A method for forming a semiconductor device which has a plurality of active region groups regularly arranged on the surface of a semiconductor substrate, and a plurality of wiring groups arranged in parallel to one another on and intersecting said plurality of active region groups and in which said plurality of active region groups are arranged and shifted from one another in the array direction of said plurality of wiring groups by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend and contact areas for each of said plurality of active region groups are each formed in an area extending in a projection form from each of said plurality of active region groups in a direction in which said plurality of wiring groups extend between adjacent wirings among said plurality of wiring groups, comprising the steps of: selectively covering said plurality of wiring groups with a first insulating film; filling a second insulating film in spaces between said plurality of wiring groups; forming a resist on said first and second insulating films and forming a resist pattern by exposing and developing the resist; selectively etching said second insulating film with respect to said first insulating film with said resist pattern used as a mask to form contact holes for the contact areas of said plurality of active region groups in said second insulating film; and forming a contact electrode wiring layer to fill said contact holes; wherein said resist pattern is formed by removing portions of said resist lying on said plurality of active region groups and said contact areas and on an area between the contact area of each of the active regions of said plurality of active region groups and another active region adjacent to said active region on the side of the projecting portion and shifted from said active region by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend.

Claim 12

A method for forming a semiconductor device which has a plurality of active region groups regularly arranged on the surface of a semiconductor substrate, an element isolation region formed between said plurality of active region groups; and a plurality of wiring groups arranged in parallel to one another on and intersecting said plurality of active region groups and in which said plurality of active region groups are arranged and shifted from one another in the array direction of said plurality of wiring groups by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend and contact areas for each of said plurality of active region groups are each formed in an area extending in a projection form from each of said plurality of active region groups in a direction in which said plurality of wiring groups extend between adjacent wirings among said plurality of wiring groups, comprising the steps of: selectively covering said plurality of wiring groups with a first insulating film; filling a second insulating film in spaces between said plurality of wiring groups; forming a resist on said first and second insulating films and forming a resist pattern by exposing and developing the resist and removing portions of the resist which lie on said plurality of active region groups and said contact areas; selectively etching said second insulating film with respect to said first insulating film with said resist pattern used as a mask to form contact holes for the contact areas of said plurality of active region groups in said second insulating film; and forming a contact electrode wiring layer to fill said contact holes; wherein said resist pattern is formed by forming said contact areas while the length X of the area extending in the projection form in said contact area in the direction in which said plurality of wiring groups extend is set to satisfy the relation of L 1 <X<2L 1 +L 2 when the width of each of said element isolation regions in the direction in which said plurality of wiring groups extend is set to L 1 and the width of one of said plurality of active regions in the above direction is set to L 2 .

Claim 13

A method for forming a semiconductor device which has a plurality of active region groups regularly arranged on the surface of a semiconductor substrate, an element isolation region formed between said plurality of active region groups; and a plurality of wiring groups arranged in parallel to one another on and intersecting said plurality of active region groups and in which said plurality of active region groups are arranged and shifted from one another in the array direction of said plurality of wiring groups by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend and contact areas for each of said plurality of active region groups are each formed in an area extending in a projection form from each of said plurality of active region groups in a direction in which said plurality of wiring groups extend between adjacent wirings among said plurality of wiring groups, comprising the steps of: selectively covering said plurality of wiring groups with a first insulating film; filling a second insulating film in spaces between said plurality of wiring groups; forming a resist on said first and second insulating films and forming a resist pattern by exposing and developing the resist and removing portions of the resist which lie on said plurality of active region groups and said contact areas; selectively etching said second insulating film with respect to said first insulating film with said resist pattern used as a mask to form contact holes for the contact areas of said plurality of active region groups in said second insulating film; and forming a contact electrode wiring layer to fill said contact holes; wherein said resist pattern is formed by forming said contact areas while the length X of the area extending in the projection form in said contact area in the direction in which said plurality of wiring groups extend is set to satisfy the relation of L 1 <X<2L 1 +L 2 when the width of each of said element isolation regions in the direction in which said plurality of wiring groups extend is set to L 1 and the width of one of said plurality of active regions in the above direction is set to L 2 .

Claim 14

A method for forming a semiconductor device which has a first area in which a plurality of first MOS transistors are formed and arranged with a first distance between gate electrodes in a channel length direction, and a second area in which a plurality of second MOS transistors having diffusion layers of impurity concentration higher than that of said first MOS transistors are formed and arranged with a second distance between gate electrodes longer than the first distance between the gate electrodes in the channel length direction, comprising the steps of: forming a conductive film on said first and second areas; selectively etching said conductive film on said first area to form and arrange a plurality of first gate electrodes with the first distance between said gate electrodes; selectively doping impurity into said first area between said first gate electrodes to form first diffusion layers; forming first gate side-wall insulating films on the side walls of said first gate electrodes; selectively etching said conductive film on said second area to form and arrange a plurality of second gate electrodes with the second distance between the gate electrodes; selectively doping impurity into said second area between said second gate electrodes to form second diffusion layers; forming second gate side-wall insulating films which are formed thicker than said first gate side-wall insulating films and formed of a different type of film from that of said first gate side-wall insulating films in contact with the side walls of said first and second gate electrodes; and selectively doping impurity into portions of said second diffusion layers which are not covered with said second gate side-wall insulating films to form third diffusion layers.

Claim 15

A method for forming a semiconductor device which has a first area in which a plurality of first MOS transistors are formed and arranged with a first distance between gate electrodes in a channel length direction, and a second area in which a plurality of second MOS transistors having diffusion layers of impurity concentration higher than that of said first MOS transistors are formed and arranged with a second distance between gate electrodes longer than the first distance between the gate electrodes in the channel length direction, comprising the steps of: forming a conductive film on said first and second areas; selectively etching said conductive film on said first area to form and arrange a plurality of first gate electrodes with the first distance between said gate electrodes; selectively doping impurity into said first area between said first gate electrodes to form first diffusion layers; forming first gate side-wall insulating films on the side walls of said first gate electrodes; selectively etching said conductive film on said second area to form and arrange a plurality of second gate electrodes with the second distance between the gate electrodes; selectively doping impurity into said second area between said second gate electrodes to form second diffusion layers; forming second gate side-wall insulating films which are formed thicker than said first gate side-wall insulating films and formed of a different type of film from that of said first gate side-wall insulating films in contact with the side walls of said first and second gate electrodes; and selectively doping impurity into portions of said second diffusion layers which are not covered with said second gate side-wall insulating films to form third diffusion layers.