US5935875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual insulating layer methods for forming integrated circuit gates and conductive contacts
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-01-21
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Granted: 1999-08-10
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Expires: 2017-01-21
Abstract
Abstract A second insulating layer is used to mask a first insulating layer on a second gate electrode, during fabrication of a conductive contact adjacent a first gate electrode which is spaced apart from the second gate electrode. By using the second insulating layer as a sacrificial insulating layer during etching of the conductive contact, thinning of the first insulating layer on the second gate electrode may be prevented. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit surface. The first and second spaced apart gate electrodes include first and second sidewalls, respectively. The first insulating layer and the second insulating layer are formed on the integrated circuit surface, including on the first and second gate electrodes. The second insulating layer is removed from the first gate. The first insulating layer is etched on the first gate to thereby form first spacers on the first sidewalls. A conductive contact is formed on the integrated circuit face, adjacent the first gate electrode and extending onto the first sidewall. The second insulating layer is removed from on the second gate and the first insulating layer is etched on the second gate, to thereby form second spacers on the second sidewalls.
Inventors
- 👤 Joo-young Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:11
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/09; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
236 words
A method for forming buffer pads of a semiconductor memory device on a semiconductor substrate including a cell array region and a peripheral circuit region, comprising the steps of: forming a plurality of gate patterns on said cell array region and on said peripheral circuit region of said semiconductor substrate; sequentially forming a first insulating film and a second insulating film on the surface of said semiconductor substrate including on said gate patterns; patterning said second insulating film to form a second insulating film pattern which exposes said first insulating film on said cell array region including on the sidewalls of said gate patterns on said cell array region; anisotropically etching said exposed first insulating film on said cell array region, to form first spacers on the sidewalls of said gate patterns on said cell array region; forming a conductive film on the surface of the semiconductor substrate, including on said gate patterns; patterning said conductive film to form buffer pads on said semiconductor substrate, between said gate patterns of said cell array region, removing said second insulating film pattern to expose said first insulating film pattern thereunder on said peripheral circuit region including on the sidewalls of said gate patterns on said peripheral circuit region; and anisotropically etching said exposed first insulating film pattern on said peripheral circuit region, to form second spacers on the sidewalls of said gate patterns on said peripheral circuit region.
Claim 2
Independent Claim
236 words
A method for forming buffer pads of a semiconductor memory device on a semiconductor substrate including a cell array region and a peripheral circuit region, comprising the steps of: forming a plurality of gate patterns on said cell array region and on said peripheral circuit region of said semiconductor substrate; sequentially forming a first insulating film and a second insulating film on the surface of said semiconductor substrate including on said gate patterns; patterning said second insulating film to form a second insulating film pattern which exposes said first insulating film on said cell array region including on the sidewalls of said gate patterns on said cell array region; anisotropically etching said exposed first insulating film on said cell array region, to form first spacers on the sidewalls of said gate patterns on said cell array region; forming a conductive film on the surface of the semiconductor substrate, including on said gate patterns; patterning said conductive film to form buffer pads on said semiconductor substrate, between said gate patterns of said cell array region, removing said second insulating film pattern to expose said first insulating film pattern thereunder on said peripheral circuit region including on the sidewalls of said gate patterns on said peripheral circuit region; and anisotropically etching said exposed first insulating film pattern on said peripheral circuit region, to form second spacers on the sidewalls of said gate patterns on said peripheral circuit region.
Claim 3
Dependent Claim
64 words
A method for forming buffer pads of a semiconductor memory device according to claim 1, wherein the step of forming a plurality of gate patterns comprises steps of: sequentially forming a gate insulating film, a conductive film and a capping insulating film on the surface of said semiconductor substrate; and sequentially patterning said capping insulating film, said conductive film and said gate insulating film.
Claim 4
Dependent Claim
25 words
A method for forming buffer pads of a semiconductor memory device according to claim 2, wherein said capping insulating film comprises a silicon oxide film.
Claim 5
Dependent Claim
25 words
A method for forming buffer pads of a semiconductor memory device according to claim 1, wherein said first insulating film comprises a silicon nitride film.
Claim 6
Dependent Claim
25 words
A method for forming buffer pads of a semiconductor memory device according to claim 1, wherein said second insulating film comprises a silicon oxide film.
Claim 7
Dependent Claim
24 words
A method for forming buffer pads of a semiconductor memory device according to claim 1, wherein said conductive film comprises a doped polysilicon film.
Claim 8
Dependent Claim
183 words
A gate electrode fabricating method for an integrated circuit comprising the steps of: forming first and second spaced apart gate electrodes on an integrated circuit surface, the first and second spaced apart gate electrodes including first and second sidewalls, respectively; forming a first insulating layer and a second insulating layer on the integrated circuit surface, including on the first and second gate electrodes; removing the second insulating layer from on the first insulating layer on the first gate to expose the first insulating layer on the first gate including on the first gate sidewalls; etching the exposed first insulating layer on the first gate, to thereby form first spacers on the first sidewalls; forming a conductive contact on the integrated circuit face, adjacent the first gate electrode, and extending onto the first sidewall; removing the second insulating layer from on the first insulating layer on the second gate to expose the first insulating layer on the second gate including on the second sidewalls; and etching the exposed first insulating layer on the second gate, to thereby form second spacers on the second sidewalls.
Claim 9
Dependent Claim
183 words
A gate electrode fabricating method for an integrated circuit comprising the steps of: forming first and second spaced apart gate electrodes on an integrated circuit surface, the first and second spaced apart gate electrodes including first and second sidewalls, respectively; forming a first insulating layer and a second insulating layer on the integrated circuit surface, including on the first and second gate electrodes; removing the second insulating layer from on the first insulating layer on the first gate to expose the first insulating layer on the first gate including on the first gate sidewalls; etching the exposed first insulating layer on the first gate, to thereby form first spacers on the first sidewalls; forming a conductive contact on the integrated circuit face, adjacent the first gate electrode, and extending onto the first sidewall; removing the second insulating layer from on the first insulating layer on the second gate to expose the first insulating layer on the second gate including on the second sidewalls; and etching the exposed first insulating layer on the second gate, to thereby form second spacers on the second sidewalls.
Claim 10
Dependent Claim
66 words
A method according to claim 7 wherein the step of forming a first insulating layer and a second insulating layer on the integrated circuit surface, including on the first and second gate electrodes, comprises the steps of: forming a first insulating layer on the integrated circuit surface, including on the first and second gate electrodes; and forming a second insulating layer on the first insulating layer.
Claim 11
Dependent Claim
23 words
A method according to claim 7 wherein the first insulating layer comprises silicon nitride and wherein the second insulating layer comprises silicon oxide.
Claim 12
Dependent Claim
33 words
A method according to claim 7 wherein the step of etching the first insulating layer on the first gate comprises the step of: anisotropically etching the first insulating layer on the first gate.
Claim 13
Dependent Claim
33 words
A method according to claim 7 wherein the step of etching the first insulating layer on the second gate comprises the step of: anisotropically etching the first insulating layer on the second gate.
Claim 14
Dependent Claim
65 words
A method according to claim 7 wherein the step of forming a conductive contact on the integrated circuit face, adjacent the first gate electrode, and extending onto the first sidewall comprises the steps of: forming a conductive layer on the integrated circuit surface including on the first gate; and etching the conductive layer from a portion of the first gate to define the conductive contact.
Claim 15
Dependent Claim
16 words
A method according to claim 7 wherein the conductive contact comprises a doped polysilicon conductive contact.
Claim 16
Dependent Claim
49 words
A method according to claim 7: wherein the integrated circuit is an integrated circuit memory device, including a cell array region and a peripheral circuit region; wherein the first gate electrode is on the cell array region; and wherein the second gate electrode is on the peripheral circuit region.
References Cited (Backward Citations)
US4484978A
Cited
US5786249A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |