US6282113B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four F-squared gapless dual layer bitline DRAM array architecture
Assignee: GlobalFoundries Inc
•
Filing: 1999-09-29
•
Granted: 2001-08-28
•
Expires: 2019-09-29
Abstract
Abstract A semiconductor device having a compact folded bitline architecture. Bitlines for a memory cell array arranged into bitline pairs constituting, when in use, a selected bitline and its complement. The selected bitline and its complement are adjacent in upper and lower levels, and exchange levels at selected breakpoints in the lower level bitline. The breakpoints are determined so as to establish a diagonally-oriented pattern of “twist regions” across the array. Adjacent bitline pairs exchange levels in alternating twist regions. The upper bitlines are positioned at a predetermined angle, relative to the lower bitlines, in selected intervals between the twist regions. The predetermined angle introduces an offset between the upper bitlines and their associated complement lower bitlines as the upper bitlines enter twist regions to exchange levels. The diagonal orientation of the twist regions, alternating pattern of breakpoints, and offsets eliminate gaps in the memory array which would otherwise be introduced in the twist regions, providing for enhanced cell density and a minimum cell area of approximately 4F 2 .
Inventors
- 👤 John K. DeBrosse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:02
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18; Y; Y10; Y10S; Y10S257/00; Y10S257/907
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
74 words
A semiconductor device comprising: an array of memory cells; and a bitline pair extending across said array and comprising a lower bitline and an upper bitline, wherein: said lower bitline is connected to said memory cells and is interrupted by breakpoints; and in selected intervals between said breakpoints, said upper bitline is positioned over said lower bitline at a predetermined angle relative thereto, and is connected to said lower bitline at said selected breakpoints.
Claim 2
Dependent Claim
74 words
A semiconductor device comprising: an array of memory cells; and a bitline pair extending across said array and comprising a lower bitline and an upper bitline, wherein: said lower bitline is connected to said memory cells and is interrupted by breakpoints; and in selected intervals between said breakpoints, said upper bitline is positioned over said lower bitline at a predetermined angle relative thereto, and is connected to said lower bitline at said selected breakpoints.
Claim 3
Dependent Claim
33 words
The semiconductor device of claim 1 , wherein: said bitline pair, when in use, constitutes a selected bitline and its complement, for reading or writing data from or to a selected memory cell.
Claim 4
Dependent Claim
72 words
The semiconductor device of claim 2 , wherein: at said breakpoints in said lower bitline, said selected bitline and said complement exchange levels, whereby: for a first extent of said lower bitline preceding a breakpoint, said selected bitline is the upper bitline and said complement is the lower bitline; and for a second extent following said selected breakpoint, said selected bitline is the lower bitline and said complement is the upper bitline.
Claim 5
Dependent Claim
19 words
The semiconductor device of claim 3 , further comprising: a plurality of said bitline pairs adjacent to each other.
Claim 6
Dependent Claim
45 words
The semiconductor device of claim 4 , wherein: a displacement is determined between breakpoints in adjacent lower bitlines so as to establish a plurality of twist regions, each twist region defining a diagonally-oriented area of said array which includes selected breakpoints in alternating lower bitlines.
Claim 7
Dependent Claim
17 words
The semiconductor device of claim 5 , wherein a bitline pair exchanges levels in alternating twist regions.
Claim 8
Dependent Claim
19 words
The semiconductor device of claim 5 , wherein adjacent bitline pairs exchange levels in separate but adjacent twist regions.
Claim 9
Dependent Claim
28 words
The semiconductor device of claim 5 , wherein: within a twist region including a breakpoint in said lower bitline, said upper bitline is offset from said lower bitline.
Claim 10
Dependent Claim
19 words
The semiconductor device of claim 8 , wherein said predetermined angle is determined so as to provide said offset.
Claim 11
Dependent Claim
21 words
The semiconductor device of claim 8 , wherein said offset is approximately 2F, where F is the minimum lithographic feature size.
Claim 12
Dependent Claim
17 words
The semiconductor device of claim 5 wherein each bitline pair passes through four or more twist regions.
Claim 13
Dependent Claim
55 words
The semiconductor device of claim 5 , said bitline pairs being connected between first and second sense amplifier banks in an alternating manner, wherein: a first bitline pair is connected to said first sense amplifier bank, and a second bitline pair adjacent to said first bitline pair is connected to said second sense amplifier bank.
Claim 14
Independent Claim
78 words
A method for increasing the density of an array of memory cells, comprising: providing a bitline pair extending across said array and comprising a lower bitline and an upper bitline, wherein: said lower bitline is connected to said memory cells and is interrupted by breakpoints; and in selected intervals between said breakpoints, said upper bitline is positioned over said lower bitline at a predetermined angle relative thereto, and is connected to said lower bitline at said selected breakpoints.
Claim 15
Independent Claim
78 words
A method for increasing the density of an array of memory cells, comprising: providing a bitline pair extending across said array and comprising a lower bitline and an upper bitline, wherein: said lower bitline is connected to said memory cells and is interrupted by breakpoints; and in selected intervals between said breakpoints, said upper bitline is positioned over said lower bitline at a predetermined angle relative thereto, and is connected to said lower bitline at said selected breakpoints.
Claim 16
Dependent Claim
32 words
The method of claim 13 , wherein: said bitline pair, when in use, constitutes a selected bitline and its complement, for reading or writing data from or to a selected memory cell.
Claim 17
Dependent Claim
71 words
The method of claim 14 , wherein: at said breakpoints in said lower bitline, said selected bitline and said complement exchange levels, whereby: for a first extent of said lower bitline preceding a breakpoint, said selected bitline is the upper bitline and said complement is the lower bitline; and for a second extent following said selected breakpoint, said selected bitline is the lower bitline and said complement is the upper bitline.
Claim 18
Dependent Claim
19 words
The method of claim 15 , further comprising: providing a plurality of said bitline pairs adjacent to each other.
Claim 19
Dependent Claim
44 words
The method of claim 16 , wherein: a displacement is determined between breakpoints in adjacent lower bitlines so as to establish a plurality of twist regions, each twist region defining a diagonally-oriented area of said array which includes selected breakpoints in alternating lower bitlines.
Claim 20
Dependent Claim
16 words
The method of claim 17 , wherein a bitline pair exchanges levels in alternating twist regions.
Claim 21
Dependent Claim
18 words
The method of claim 17 , wherein adjacent bitline pairs exchange levels in separate but adjacent twist regions.
Claim 22
Dependent Claim
27 words
The method of claim 17 , wherein: within a twist region including a breakpoint in said lower bitline, said upper bitline is offset from said lower bitline.
Claim 23
Dependent Claim
18 words
The method of claim 20 , wherein said predetermined angle is determined so as to provide said offset.
Claim 24
Dependent Claim
20 words
The method of claim 20 , wherein said offset is approximately 2F, where F is the minimum lithographic feature size.
References Cited (Backward Citations)
US4402063A
Cited
US5416734A
Cited
US5194752A
Cited
US5107459A
Cited
US5315542A
Cited
US5821592A
Cited
US5864496A
Cited
US6108230A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |