Patent US6256770B1 successfully refreshed from Google Patents.
US6256770B1
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US
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Register transfer level (RTL) based scan insertion for integrated circuit design processes
Assignee: Nokia of America Corp
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Filing: 1997-10-17
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Granted: 2001-07-03
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Expires: 2017-10-17
Abstract
Abstract A design-level description of a circuit is processed to incorporate testability functions in the form of scan chains. The design-level description may be a Register Transfer Level (RTL) description in accordance with the VHDL standard. The design-level description includes processes describing operations of the circuit. The processes are analyzed to identify data carriers in the design-level description which correspond to flip-flops or other specified elements in the circuit. The specified elements are organized into scan chains, which are then allocated to appropriate modules of the circuit. Scan ordering and scan insertion operations are performed separately on each of the modules. The scan ordering operation is based on functional relationships between the data carriers in the processes associated with the modules. The functional relationships can include both word-level and bit-level dependencies. The scan insertion operation involves inserting scan assignment statements into the processes. The modified design-level descriptions of the modules are separately synthesized to generate gate-level descriptions of the circuit modules, such that the overall circuit includes the appropriate scan chains.
Inventors
- 👤 David Anthony Pierce
- 👤 Subrata Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:59
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318586; G01R31/3183; G01R31/318364
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
232 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering scan chain representations for at least a given one of the modules of the circuit based on a functional relationship between data carriers in one or more of the hardware description language processes, wherein the data carriers correspond to specific types of elements in the circuit, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 2
Independent Claim
232 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering scan chain representations for at least a given one of the modules of the circuit based on a functional relationship between data carriers in one or more of the hardware description language processes, wherein the data carriers correspond to specific types of elements in the circuit, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 3
Dependent Claim
43 words
The method of claim 1 further including the steps of: analyzing the processes to identify the data carriers in the design-level description which correspond to specific types of elements in the circuit; and generating the scan chain representations using the identified data carriers.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein the design-level description is an RTL VHDL description.
Claim 5
Dependent Claim
32 words
The method of claim 2 wherein the step of analyzing the processes to identify data carriers further includes analyzing the processes to identify data carriers that correspond to flip-flops in the circuit.
Claim 6
Dependent Claim
20 words
The method of claim 2 wherein the step of analyzing the processes further includes locating clocking statements within the processes.
Claim 7
Dependent Claim
28 words
The method of claim 2 wherein the generating step further includes the step of allocating different portions of the scan chain representations to different modules of the circuit.
Claim 8
Dependent Claim
22 words
The method of claim 6 wherein the ordering and inserting steps are performed separately on each of the modules of the circuit.
Claim 9
Dependent Claim
51 words
The method of claim 1 wherein the functional relationships between data carriers in a given process are analyzed in the form of a signal-variable graph which includes edges of the form (n 1 , n 2 ) where n 1 and n 2 are signals or variables in the given process.
Claim 10
Dependent Claim
33 words
The method of claim 8 wherein edges of the signal-variable graph corresponding to a direct assignment are assigned a first priority, and all other edges are assigned priorities lower than the first priority.
Claim 11
Dependent Claim
34 words
The method of claim 8 wherein the signal-variable graph for the processes associated with an entity of the high-level description is used in the ordering step to order scan chains having desired chain lengths.
Claim 12
Dependent Claim
33 words
The method of claim 1 wherein the data carriers include variables and signals, such that variables are local to a given process and signals are used for communication between two or more processes.
Claim 13
Dependent Claim
24 words
The method of claim 1 wherein the ordering step includes ordering the scan chains based on both word-level and bit-level dependencies in the processes.
Claim 14
Dependent Claim
30 words
The method of claim 1 further including the step of utilizing built-in self test circuitry within the circuit to process test signals applied to and output from the scan chains.
Claim 15
Dependent Claim
30 words
The method of claim 1 further including the step of utilizing automated test equipment external to the circuit to process test signals applied to and output from the scan chains.
Claim 16
Independent Claim
264 words
An apparatus for implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the apparatus comprising: a memory for storing at least a portion of the design-level description; and at least one processor coupled to the memory, wherein the at least one processor is operative: (1) to allocate portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; (2) to order scan chain representations for at least a given one of the modules of the circuit based on a functional relationship between data carriers in one or more of the hardware description language processes, wherein the data carriers correspond to specific types of elements in the circuit, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and (3) to insert scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 17
Independent Claim
264 words
An apparatus for implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the apparatus comprising: a memory for storing at least a portion of the design-level description; and at least one processor coupled to the memory, wherein the at least one processor is operative: (1) to allocate portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; (2) to order scan chain representations for at least a given one of the modules of the circuit based on a functional relationship between data carriers in one or more of the hardware description language processes, wherein the data carriers correspond to specific types of elements in the circuit, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and (3) to insert scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 18
Dependent Claim
46 words
The apparatus of claim 15 wherein the processor is further operative to analyze the processes to identify data carriers in the design-level description which correspond to specific types of elements in the circuit, and to generate the scan chain representations based on the identified data carriers.
Claim 19
Dependent Claim
14 words
The apparatus of claim 15 wherein the design-level description is an RTL VRDL description.
Claim 20
Dependent Claim
25 words
The apparatus of claim 16 wherein the processor is operative to analyze the processes to identify data carriers that correspond to flip-flops in the circuit.
Claim 21
Dependent Claim
20 words
The apparatus of claim 16 wherein the processor is operative to analyze the processes locating clocking statements within the processes.
Claim 22
Dependent Claim
38 words
The apparatus of claim 15 wherein the processor is operative to allocate different portions of the scan chain representations to different modules of the circuit, such that the order and insert operations are applied separately to different modules.
Claim 23
Dependent Claim
51 words
The apparatus of claim 15 wherein the processor is operative to analyze functional relationships between data carriers in a given process using a signal-variable graph which includes edges of the form (n 1 , n 2 ) where n 1 and n 2 are signals or variables in the given process.
Claim 24
Dependent Claim
33 words
The apparatus of claim 21 wherein edges of the signal-variable graph corresponding to a direct assignment are assigned a first priority, and all other edges are assigned priorities lower than the first priority.
Claim 25
Dependent Claim
33 words
The apparatus of claim 21 wherein the signal-variable graph for the processes associated with an entity of the high-level description is used by the processor to order scan chains having desired chain lengths.
Claim 26
Dependent Claim
33 words
The apparatus of claim 15 wherein the data carriers include variables and signals, such that variables are local to a given process and signals are used for communication between two or more processes.
Claim 27
Dependent Claim
25 words
The apparatus of claim 15 wherein the processor is operative to order the scan chains based on both word-level and bit-level dependencies in the processes.
Claim 28
Independent Claim
233 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering scan chain representations for at least a given one of the modules of the circuit based on functional relationships between data carriers in one or more of the hardware description language processes, the functional relationships including both word-level and bit-level dependencies in the hardware description language processes, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 29
Independent Claim
233 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering scan chain representations for at least a given one of the modules of the circuit based on functional relationships between data carriers in one or more of the hardware description language processes, the functional relationships including both word-level and bit-level dependencies in the hardware description language processes, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.
Claim 30
Independent Claim
195 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering the scan chain representations for each of the modules of the circuit based on functional relationships between data carriers in one or more of the hardware description language processes; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying one or more synthesis processes to the design-level description of the modules of the circuit, such that a gate-level description of the circuit generated by the one or more synthesis processes applied to the design-level description includes the specified scan chains for use in testing the circuit, wherein the ordering and inserting steps are performed separately on each of the modules of the circuit.
Claim 31
Independent Claim
195 words
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of: allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules; ordering the scan chain representations for each of the modules of the circuit based on functional relationships between data carriers in one or more of the hardware description language processes; and inserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying one or more synthesis processes to the design-level description of the modules of the circuit, such that a gate-level description of the circuit generated by the one or more synthesis processes applied to the design-level description includes the specified scan chains for use in testing the circuit, wherein the ordering and inserting steps are performed separately on each of the modules of the circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |