System and method for improving fault coverage of an electric circuit

Claim 1

A computer implemented method for selecting testpoints to increase overall fault coverage of an electrical circuit, said computer including a memory and a display, comprising the steps of: providing a netlist of a plurality of circuit design cells describing said electrical circuit in said memory of said computer, said netlist identifying a plurality of nodes and a plurality of connections between said plurality of nodes; generating a scan path through said plurality of circuit design cells and said plurality of nodes in said netlist in response to a user request comprising the steps of ordering said plurality of circuit design cells to be scanned and inserting dummy scan cells into said scan path to eliminate register adjacency; determining a fault grade associated with each of said plurality of nodes included in said scan path through said netlist; measuring potential effectiveness of insertion of a testpoint at each of said plurality of nodes in response to said determining step; selecting a first set of testpoints that enhance controllability of said electrical circuit described in said netlist in response to said measuring step; selecting a second set of testpoints that enhance observability of said electrical circuit described in said netlist in response to said measuring step; ranking said first set of testpoints and said second set of testpoints in accordance with said potential effectiveness thereby generating a third set of testpoints, each of said testpoints having an associated rank; and repeatedly inserting one of said testpoints included in said third set of testpoints into said netlist in accordance with said associated rank until a desired fault coverage for said electrical circuit described in said netlist is obtained, thereby generating an updated netlist.