US5390193A
Expired / Lapsed
US
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Test pattern generation
Assignee: NXP USA Inc
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Filing: 1992-10-28
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Granted: 1995-02-14
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Expires: 2012-10-28
Abstract
Abstract A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).
Inventors
- 👤 Steven D. Millman
- 👤 James P. Garvey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:10
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
281 words
A method for generating and simulating test patterns to detect faults in an integrated circuit, comprising: identifying a plurality of nets which can potentially be shorted together as a plurality of potential faults; listing each potential fault in a fault list; categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault wherein categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault includes: assigning a level to a gate output node equal to the greatest number of intervening gates between the gate output node and a primary input; placing an identification code for each gate output node in a linked list which corresponds to the level of the gate output node; building a dependency list for each gate output node comprising the identification codes for each node on a path between the gate's output node and a primary input; recursively adding the dependency list for each gate which drives an input node to the gate until all dependencies are included; selecting a potential fault from the fault list; inspecting the nodes to determine a high level faulty node and a low level faulty node from the nodes which comprises the potential fault; and inspecting the dependency list associated with the high level faulty node to determine if the potential fault creates a feedback fault; selecting one potential fault from the fault list, having a first faulty node and a second faulty node; generating a test pattern to detect the selected potential fault; and checking the test pattern to ensure that the selected potential fault is detected even if the potential fault is categorized as a feedback fault.
Claim 2
Independent Claim
281 words
A method for generating and simulating test patterns to detect faults in an integrated circuit, comprising: identifying a plurality of nets which can potentially be shorted together as a plurality of potential faults; listing each potential fault in a fault list; categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault wherein categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault includes: assigning a level to a gate output node equal to the greatest number of intervening gates between the gate output node and a primary input; placing an identification code for each gate output node in a linked list which corresponds to the level of the gate output node; building a dependency list for each gate output node comprising the identification codes for each node on a path between the gate's output node and a primary input; recursively adding the dependency list for each gate which drives an input node to the gate until all dependencies are included; selecting a potential fault from the fault list; inspecting the nodes to determine a high level faulty node and a low level faulty node from the nodes which comprises the potential fault; and inspecting the dependency list associated with the high level faulty node to determine if the potential fault creates a feedback fault; selecting one potential fault from the fault list, having a first faulty node and a second faulty node; generating a test pattern to detect the selected potential fault; and checking the test pattern to ensure that the selected potential fault is detected even if the potential fault is categorized as a feedback fault.
Claim 3
Dependent Claim
62 words
The method for generating and simulating test patterns to detect faults in an integrated circuit according to claim 1, further comprising: implicitly determining the potential feedback fault category as either potential odd inversion feedback faults or potential even inversion feedback faults; testing each potential odd inversion feedback fault for oscillation; and testing each potential even inversion feedback fault for a latch state.
Claim 4
Dependent Claim
168 words
The method for generating and simulating test patterns to detect faults in an integrated circuit according to claim 1, wherein identifying a plurality of nets which can potentially be shorted together as a plurality of potential faults comprises: providing a plurality of nets each net having a plurality of destinations having a predetermined minimum routing distance and a predetermined actual routing distance; forming a list comprising the plurality of nets; selecting one net from the list; removing the selected net from the list; computing an excess wire length for the selected net based on the difference between the predetermined minimum routing distance and the predetermined actual routing distance of the selected net; determining the maximum excursion of the wire routing to obtain a bounding distance; forming a rectilinear bounding box including each destination for the selected net and extending at least the bounding distance beyond any destination; and identifying all nets which intersect the rectilinear bounding box as nets which can potentially be shorted to the selected net.
Claim 5
Dependent Claim
136 words
The method for generating and simulating test patterns to detect faults in an integrated circuit according to claim 1, wherein identifying a plurality of nets which can potentially be shorted together as a plurality of potential faults comprises: providing a plurality of nets each net having a plurality of destinations and a predetermined physical routing distance; computing an excess wire length for each net based on the physical routing distance of the net; dividing the excess wire length by two to obtain a bounding distance for the net; forming a rectilinear bounding box which includes each destination for each net and extends at least the bounding distance beyond any destination; listing each rectilinear bounding box; and identifying the pair of nets associated with each intersecting bounding box as two nets which can potentially be shorted together.
Claim 6
Independent Claim
145 words
A method for categorizing faults in an integrated circuit comprising: assigning a level to a gate output node equal to the greatest number of intervening gates between the gate output node and a primary input; placing an identification code for each gate output node in a linked list which corresponds to the level of the gate output node; building a dependency list for each gate output node comprising the identification codes for each node on a path between the gate's output node and a primary input; selecting a potential fault from a fault list; inspecting the nodes which comprise the potential fault to determine a high level faulty node and a low level faulty node from the nodes which comprises the potential fault; and inspecting the dependency list associated with the high level faulty node to determine if the potential fault creates a feedback fault.
Claim 7
Independent Claim
145 words
A method for categorizing faults in an integrated circuit comprising: assigning a level to a gate output node equal to the greatest number of intervening gates between the gate output node and a primary input; placing an identification code for each gate output node in a linked list which corresponds to the level of the gate output node; building a dependency list for each gate output node comprising the identification codes for each node on a path between the gate's output node and a primary input; selecting a potential fault from a fault list; inspecting the nodes which comprise the potential fault to determine a high level faulty node and a low level faulty node from the nodes which comprises the potential fault; and inspecting the dependency list associated with the high level faulty node to determine if the potential fault creates a feedback fault.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |