US5812561A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scan based testing of an integrated circuit for compliance with timing specifications
Assignee: NXP USA Inc
•
Filing: 1996-09-03
•
Granted: 1998-09-22
•
Expires: 2016-09-03
Abstract
Abstract A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.
Inventors
- 👤 Grady L. Giles
- 👤 Alfred Larry Crouch
- 👤 Odis Dale Amason, Jr.
- 👤 Matthew Donald Pressly
- 👤 Clark Gilson Shepard
- 👤 Michael Alan Mateja
- 👤 Lee Allen Corley
- 👤 Daniel T. Marquette
- 👤 Jason E. Doege
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318572; G01R31/318577; G01R31/31858
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
205 words
A method for testing timing specifications for an integrated circuit, said integrated circuit having functional circuit paths including sequential circuit elements therein, said functional circuit paths being designed to implement a specified functional specification and provide functional output signals at output terminals of said integrated circuit, said method comprising the steps of: providing a scan path on said integrated circuit, said scan path being selectively routed on said integrated circuit among selected sequential circuit elements, said scan path being terminated at said integrated circuit output terminals, said integrated circuit input/output terminals also being arranged to selectively provide functional output signals for said functional circuit paths; applying a first testing signal to said integrated circuit, said first testing signal being operable to effect a testing signal propagation through said scan path and provide a timing output signal at one of said integrated circuit output terminals; and applying a second testing signal to said integrated circuit, said second testing signal being applied independently of the first testing signal and independently of the sequential circuit elements, the second testing signal operable to control when the output terminal is used to provide the functional output signals and when the output terminal is used to provide the timing output signal.
Claim 2
Independent Claim
205 words
A method for testing timing specifications for an integrated circuit, said integrated circuit having functional circuit paths including sequential circuit elements therein, said functional circuit paths being designed to implement a specified functional specification and provide functional output signals at output terminals of said integrated circuit, said method comprising the steps of: providing a scan path on said integrated circuit, said scan path being selectively routed on said integrated circuit among selected sequential circuit elements, said scan path being terminated at said integrated circuit output terminals, said integrated circuit input/output terminals also being arranged to selectively provide functional output signals for said functional circuit paths; applying a first testing signal to said integrated circuit, said first testing signal being operable to effect a testing signal propagation through said scan path and provide a timing output signal at one of said integrated circuit output terminals; and applying a second testing signal to said integrated circuit, said second testing signal being applied independently of the first testing signal and independently of the sequential circuit elements, the second testing signal operable to control when the output terminal is used to provide the functional output signals and when the output terminal is used to provide the timing output signal.
Claim 3
Dependent Claim
22 words
The method as set forth in claim 1 and further including validating said timing output signal from said integrated circuit output terminals.
Claim 4
Dependent Claim
17 words
The method as set forth in claim 2, wherein said sequential circuit element is a latching circuit.
Claim 5
Dependent Claim
17 words
The method as set forth in claim 2, wherein said sequential circuit element is a flip-flop circuit.
Claim 6
Dependent Claim
31 words
The method as set forth in claim 2, wherein said method further includes: switching from said scan path to said functional circuit path following said validating of said timing output signal.
Claim 7
Dependent Claim
33 words
The method as set forth in claim 2, wherein said method further includes: switching from said functional circuit path to said scan path following a predetermined delay time of said timing output signal.
Claim 8
Dependent Claim
42 words
The method as set forth in claim 2, wherein said integrated circuit further includes at least one tristate device for driving at least one signal line, said method further including selectively enabling and disabling said tristate device during said testing signal propagation.
Claim 9
Dependent Claim
275 words
An integrated circuit comprising: a plurality of input terminals; a plurality of output terminals; logic circuitry connected between said input terminals and said output terminals, said logic circuitry defining a functional circuit path, said logic circuitry including at least one sequential circuit element, said logic circuitry being selectively operable to implement a functional specification for said integrated circuit through a functional circuit path to provide functional output signals at said output terminals; and testing signal circuitry connected between said input terminals and said output terminals, said testing signal circuitry defining a testing circuit path, a scan enable signal being applied to said test signal circuitry for controlling shifting of the test data through said testing circuit path, said testing signal circuitry further including a first switching device connecting one of said input terminals to an input terminal of said sequential circuit element, and a second switching device connecting an output terminal of said sequential circuit element to one of said integrated circuit output terminals, said first switching device and said second switching device being controlled by a bus scan enable signal, the bus scan enable signal being applied independently of both the scan enable signal and the at least one sequential circuit element, the bus scan enable signal is operable to control when the plurality of input terminals are used to receive the functional input signals, and to control when the plurality of output terminals are to provide the functional output signals, and to control when the plurality of output terminals are to provide the test data, wherein the use of bus scan enable signal is for implementing a timing analysis of the integrated circuit.
Claim 10
Dependent Claim
275 words
An integrated circuit comprising: a plurality of input terminals; a plurality of output terminals; logic circuitry connected between said input terminals and said output terminals, said logic circuitry defining a functional circuit path, said logic circuitry including at least one sequential circuit element, said logic circuitry being selectively operable to implement a functional specification for said integrated circuit through a functional circuit path to provide functional output signals at said output terminals; and testing signal circuitry connected between said input terminals and said output terminals, said testing signal circuitry defining a testing circuit path, a scan enable signal being applied to said test signal circuitry for controlling shifting of the test data through said testing circuit path, said testing signal circuitry further including a first switching device connecting one of said input terminals to an input terminal of said sequential circuit element, and a second switching device connecting an output terminal of said sequential circuit element to one of said integrated circuit output terminals, said first switching device and said second switching device being controlled by a bus scan enable signal, the bus scan enable signal being applied independently of both the scan enable signal and the at least one sequential circuit element, the bus scan enable signal is operable to control when the plurality of input terminals are used to receive the functional input signals, and to control when the plurality of output terminals are to provide the functional output signals, and to control when the plurality of output terminals are to provide the test data, wherein the use of bus scan enable signal is for implementing a timing analysis of the integrated circuit.
Claim 11
Dependent Claim
63 words
The integrated circuit as set forth in claim 8, wherein said first and second switching devices are selectively operable to switch between a first position effective to complete said functional circuit path between said input terminals and said output terminals, and a second position effective to complete said testing circuit between said input terminals and said output terminals path during a testing cycle.
Claim 12
Dependent Claim
65 words
The integrated circuit as set forth in claim 9, wherein said functional circuit path further includes at least one tristate device arranged to selectively drive at least one signal line, said integrated circuit further including a signal generating device for generating a disable signal, said disable signal being effectively applied to said tristate device to selectively disable said tristate device during said testing signal propagation.
Claim 13
Dependent Claim
62 words
The integrated circuit as set forth in claim 8, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.
Claim 14
Dependent Claim
62 words
The integrated circuit as set forth in claim 9, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.
Claim 15
Dependent Claim
62 words
The integrated circuit as set forth in claim 10, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.
Claim 16
Dependent Claim
28 words
The integrated circuit as set forth in claim 13, wherein said shared output terminal is a bidirectional terminal for providing an input signal to said functional circuit path.
Claim 17
Dependent Claim
39 words
The integrated circuit as set forth in claim 8, wherein said first switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.
Claim 18
Dependent Claim
39 words
The integrated circuit as set forth in claim 8, wherein said second switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.
Claim 19
Dependent Claim
39 words
The integrated circuit as set forth in claim 15, wherein said second switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.
Claim 20
Dependent Claim
43 words
The integrated circuit as set forth in claim 8, wherein said integrated circuit includes a plurality of sequential circuit elements, said integrated circuit further including a like plurality of each of said first and second switching devices connected to said sequential circuit elements.
Claim 21
Dependent Claim
36 words
The integrated circuit as set forth in claim 8, wherein said testing signal circuitry further includes a head register device connected between said one of said input terminals and said input terminal of said sequential element.
Claim 22
Dependent Claim
25 words
The integrated circuit as set forth in claim 19, wherein said head register device is comprised of at least one head register sequential logic device.
Claim 23
Dependent Claim
24 words
The integrated circuit as set forth in claim 20, wherein said head register sequential logic device is comprised of at least one flip-flop circuit.
Claim 24
Dependent Claim
38 words
The integrated circuit as set forth in claim 19, wherein said testing signal circuitry further includes a tail register device connected at an end of the testing circuit path for adding delay time for the testing circuit path.
References Cited (Backward Citations)
US5132974A
Cited
US5260949A
Cited
US5604432A
Cited
US5467354A
Cited
US5535223A
Cited
US5526365A
Cited
US5592493A
Cited
US5633879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |