Short write test mode for testing static memory cells

Claim 3

The apparatus of claim 1 wherein said short write test circuit is further to hold the second bit line to a supply voltage level.

Claim 4

The apparatus of claim 1 wherein said stress is a strong stress that, if applied for a sufficient duration, overwrites said stored value.

Claim 5

The apparatus of claim 2 wherein said short write test circuit is to drive said first bit line to an intermediate level that is determined to be higher than a trip point for a good cell.

Claim 6

The apparatus of claim 2 further wherein said short write test circuit is also to provide a second stress to the memory cell on the second bit line while holding the first bit line to the supply voltage level.

Claim 7

The apparatus of claim 1 wherein said short write test circuit comprises: a programmable delay line; a current source coupled to said first bit line and coupled to the programmable delay line to drive the first bit line toward a ground level for the programmable duration; and a pullup transistor coupled to said second bit line.

Claim 8

The apparatus of claim 6 wherein said current source comprises: a pass transistor coupled to said first bit line; a pulldown transistor coupled to said pass transistor and to a ground voltage supply.

Claim 9

The apparatus of claim 7 wherein said memory cell includes a first memory cell pass transistor and a first memory cell pulldown transistor and wherein said pass transistor and said pulldown transistor are sized identically to respectively said first memory cell pass transistor and said first memory cell pulldown transistor.

Claim 10

The apparatus of claim 6 further comprising: a second current source coupled to said second bit line and coupled to the programmable delay line to drive the second bit line to the ground level for the programmable duration as a part of a second short write test; a second pullup transistor coupled to the first bit line, wherein said current source and said pullup transistor are to be enabled in a short write 0 test mode and said second pullup transistor and said second current source are to be enabled in a short write 1 test mode.

Claim 13

The method of claim 10 further comprising: applying a supply voltage to a second bit line.

Claim 14

The method of claim 10 wherein stressing comprises: enabling a test transistor of equivalent size to a memory cell transistor for the programmable duration.

Claim 15

The method of claim 12 wherein enabling comprises: enabling a test pulldown transistor and a test pass gate of equivalent sizes to pass gates and pulldown transistors in said static memory cell.

Claim 16

The method of claim 10 wherein stressing comprises: applying a strong stress that, if applied for a sufficient duration, is sufficiently strong to overwrite a value stored in said static memory cell.

Claim 17

A static random access memory comprising: a plurality of memory cells; a programmable short write test pulse generator; a short write test circuit to stress each of said plurality of memory cells with a strong stress sufficient to overwrite values stored in said plurality of memory cells, said strong stress being programmable in strength by adjusting a pulse length generated by said programmable short write test pulse generator, wherein said short write test circuit includes stress transistors of identical size to those in the plurality of memory cells.

Claim 18

A static random access memory comprising: a plurality of memory cells; a programmable short write test pulse generator; a short write test circuit to stress each of said plurality of memory cells with a strong stress sufficient to overwrite values stored in said plurality of memory cells, said strong stress being programmable in strength by adjusting a pulse length generated by said programmable short write test pulse generator, wherein said short write test circuit includes stress transistors of identical size to those in the plurality of memory cells.

Claim 19

The static random access memory of claim 15 wherein said short write test circuit applies a stress voltage to a first bit line during a first short write test.

Claim 20

The static random access memory of claim 16 wherein said short write test circuit applies a supply voltage to a second bit line during the first short write test.

Claim 21

The static random access memory of claim 17 wherein said short write test circuit applies a second stress voltage to the second bit line during a second short write test.

Claim 22

The static random access memory of claim 18 wherein said short write test circuit applies the supply voltage to the first bit line during the second short write test.