US6252290B1
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US
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Method to form, and structure of, a dual damascene interconnect device
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1999-10-25
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Granted: 2001-06-26
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Expires: 2019-10-25
Abstract
Abstract A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.
Inventors
- 👤 Shyue Fong Quek
- 👤 Ting Cheong Ang
- 👤 Lap Chan
- 👤 Sang Yee Loong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072; H10W20/081; H10W20/084; H10W20/40; H10W20/45; H10W20/46; H10W20/0884
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
288 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) depositing and exposing a first level via photo sensitive dielectric layer over a semiconductor structure; b) depositing and exposing a first level trench photo sensitive dielectric layer over said first via photo sensitive dielectric layer; c) patterning and etching said exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and trench line openings; d) depositing a first level conductor layer over said first level trench photo sensitive dielectric layer, filling said first level dual damascene opening; e) planarizing said first level trench layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; f) repeating steps a) to e) over said first level dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of conductor dual damascene interconnects; g) depositing and patterning a passivation layer over said nth conductor dual damascene interconnect layer to form openings in said passivation layer; and h) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric layer underneath said horizontal metal lines of said stripped trench photo sensitive dielectric layers remains.
Claim 2
Independent Claim
288 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) depositing and exposing a first level via photo sensitive dielectric layer over a semiconductor structure; b) depositing and exposing a first level trench photo sensitive dielectric layer over said first via photo sensitive dielectric layer; c) patterning and etching said exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and trench line openings; d) depositing a first level conductor layer over said first level trench photo sensitive dielectric layer, filling said first level dual damascene opening; e) planarizing said first level trench layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; f) repeating steps a) to e) over said first level dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of conductor dual damascene interconnects; g) depositing and patterning a passivation layer over said nth conductor dual damascene interconnect layer to form openings in said passivation layer; and h) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric layer underneath said horizontal metal lines of said stripped trench photo sensitive dielectric layers remains.
Claim 3
Dependent Claim
46 words
The method of claim 1 , wherein said first level and subsequent via photo sensitive dielectric layers have a thickness from about 7000 to 14,000 Å, and said first level and subsequent trench photo sensitive dielectric layers have a thickness from about 4000 to 7000 Å.
Claim 4
Dependent Claim
25 words
The method of claim 1 , wherein said conductor is selected from the group comprising aluminum, copper, a copper alloy, an aluminum alloy, and tungsten.
Claim 5
Dependent Claim
49 words
The method of claim 1 , further including the step of forming a barrier layer within said first level and subsequent level dual damascene opening before said metal layer deposition step, wherein said barrier layer is comprised of a conductor selected from the group TaN, TiN, Ta, and TaSiN.
Claim 6
Dependent Claim
44 words
The method of claim 1 , wherein said passivation layer is comprised of a material selected from the dielectric group consisting of Si 3 N 4 , polyimide, SiO 2 , phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), SABPSAG, Undoped Silicate Glass (USG) and FSG.
Claim 7
Dependent Claim
19 words
The method of claim 1 , wherein air gaps are formed between adjacent said plurality of dual damascene structures.
Claim 8
Independent Claim
318 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) depositing and exposing a first level via photo sensitive dielectric layer, having a thickness from about 7000 to 14,000 Å, over a semiconductor structure; b) depositing and exposing a first level trench photo sensitive dielectric layer, having a thickness from about 4000 to 7000 Å, over said first via photo sensitive dielectric layer; c) patterning and etching said exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and metal line openings; d) forming a barrier layer within said first level dual damascene opening; e) depositing a first level conductor layer over said first level trench photo sensitive dielectric layer, filling said first level dual damascene opening; f) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; g) repeating steps a) to f) over said first level metal dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects; h) depositing and patterning a passivation layer over said nth conductor dual damascene interconnect layer to form openings in said passivation layer; and i) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal metal lines of said stripped trench photo sensitive dielectric layers remains.
Claim 9
Independent Claim
318 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) depositing and exposing a first level via photo sensitive dielectric layer, having a thickness from about 7000 to 14,000 Å, over a semiconductor structure; b) depositing and exposing a first level trench photo sensitive dielectric layer, having a thickness from about 4000 to 7000 Å, over said first via photo sensitive dielectric layer; c) patterning and etching said exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and metal line openings; d) forming a barrier layer within said first level dual damascene opening; e) depositing a first level conductor layer over said first level trench photo sensitive dielectric layer, filling said first level dual damascene opening; f) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; g) repeating steps a) to f) over said first level metal dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects; h) depositing and patterning a passivation layer over said nth conductor dual damascene interconnect layer to form openings in said passivation layer; and i) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal metal lines of said stripped trench photo sensitive dielectric layers remains.
Claim 10
Dependent Claim
25 words
The method of claim 7 , wherein said conductor is selected from the group comprising aluminum, copper, a copper alloy, an aluminum alloy, and tungsten.
Claim 11
Dependent Claim
25 words
The method of claim 7 , wherein said barrier layer is comprised of a conductor selected from the group TaN, TiN, Ta, TaSiN, and TiW.
Claim 12
Dependent Claim
38 words
The method of claim 7 , wherein said passivation layer is comprised of a material selected from the group consisting of Si 3 N 4 , SiO 2 , PSG, BPSG, SABPSAG, TEOS Oxide, BPTEOS, USG and FSG.
Claim 13
Dependent Claim
19 words
The method of claim 7 , wherein air gaps are formed between adjacent said plurality of dual damascene structures.
Claim 14
Independent Claim
250 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) spinning on, exposing, developing and ashing a first level photo sensitive dielectric layer over a semiconductor structure to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and metal line openings; b) depositing a first level conductor layer over said first level photo sensitive dielectric layer, filling said first level dual damascene opening; c) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; d) repeating steps a) to c) over said first level dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects; e) depositing and patterning a passivation layer over said nth metal dual damascene interconnect layer to form openings in said passivation layer; and f) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal conductor lines of said stripped trench photo sensitive dielectric layers. remains.
Claim 15
Independent Claim
250 words
A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprising the steps of: a) spinning on, exposing, developing and ashing a first level photo sensitive dielectric layer over a semiconductor structure to form a first level dual damascene opening; said first level dual damascene opening comprising an integral first level via and metal line openings; b) depositing a first level conductor layer over said first level photo sensitive dielectric layer, filling said first level dual damascene opening; c) planarizing said first level conductor layer to form at least one first level dual damascene interconnect, said first level dual damascene interconnect having a first level horizontal conductor line and a first level vertical via stack; d) repeating steps a) to c) over said first level dual damascene interconnect n-1 times to form a dual damascene interconnect structure where n is the number of interconnect levels desired, and where a plurality of dual damascene structures may be formed having from n to n-1 levels of metal dual damascene interconnects; e) depositing and patterning a passivation layer over said nth metal dual damascene interconnect layer to form openings in said passivation layer; and f) selectively stripping and removing a predetermined number of said via photo sensitive dielectric and trench photo sensitive dielectric layers beneath said passivation layer openings and between said plurality of dual damascene structures wherein the portion of said via photo sensitive dielectric underneath said horizontal conductor lines of said stripped trench photo sensitive dielectric layers. remains.
Claim 16
Dependent Claim
85 words
An interconnect structure in a semiconductor device comprising; a semiconductor layer; at least one interconnect structure comprising a plurality of interconnects above said semiconductor layer; each said interconnect having a horizontal conductor line and a vertical via stack; air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers; and polymer supports under said conductor lines and adjacent said via stacks of said interconnects; whereby said polymer supports support and strengthen said at least one interconnect structure.
Claim 17
Dependent Claim
85 words
An interconnect structure in a semiconductor device comprising; a semiconductor layer; at least one interconnect structure comprising a plurality of interconnects above said semiconductor layer; each said interconnect having a horizontal conductor line and a vertical via stack; air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers; and polymer supports under said conductor lines and adjacent said via stacks of said interconnects; whereby said polymer supports support and strengthen said at least one interconnect structure.
Claim 18
Dependent Claim
14 words
The interconnect structure of claim 13 , wherein said interconnects are dual damascene interconnects.
Claim 19
Dependent Claim
39 words
The interconnect structure of claim 13 , wherein said polymer supports are comprised of a material selected from the group consisting of UV photoresist series, PFI photoresist series, and polymer low-k dielectric like BCB, parylene, HSQ, MSQ and XEROGEL.
Claim 20
Dependent Claim
25 words
The interconnect structure of claim 13 , wherein said plurality of interconnects are comprised of aluminum, copper, a copper alloy, aluminum, an aluminum alloy, tungsten.
Claim 21
Dependent Claim
27 words
The interconnect structure of claim 13 , wherein said polymer supports are comprised of a low-k material having a dielectric constant of between about 1.5 and 3.9.
Claim 22
Dependent Claim
27 words
The interconnect structure of claim 13 , wherein said polymer supports are comprised of a low-k material having a dielectric constant of between about 2.5 and 3.2.
Claim 23
Dependent Claim
94 words
An interconnect structure in a semiconductor device comprising; a semiconductor layer; at least one interconnect structure comprising a plurality of dual damascene copper interconnects above said semiconductor layer; each said dual damascene copper interconnect having a horizontal conductor line and a vertical via stack; air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers; and polymer supports under said conductor lines and adjacent said via stacks of said dual damascene copper interconnects; whereby said polymer supports support and strengthen said at least one interconnect structure.
Claim 24
Dependent Claim
94 words
An interconnect structure in a semiconductor device comprising; a semiconductor layer; at least one interconnect structure comprising a plurality of dual damascene copper interconnects above said semiconductor layer; each said dual damascene copper interconnect having a horizontal conductor line and a vertical via stack; air gaps adjacent said at least one interconnect structure, said air gaps formed within the interlevel and intralevel layers; and polymer supports under said conductor lines and adjacent said via stacks of said dual damascene copper interconnects; whereby said polymer supports support and strengthen said at least one interconnect structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-25 | 2004-12-25 | 2005-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-25 | 2008-12-25 | 2009-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-25 | 2012-12-25 | 2013-06-26 | $7700.00 | Window Closed / Lapsed |