Patent US6251694B1 successfully refreshed from Google Patents.
US6251694B1
Expired / Lapsed
US
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Method of testing and packaging a semiconductor chip
Assignee: United Microelectronics Corp
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Filing: 1999-05-26
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Granted: 2001-06-26
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Expires: 2019-05-26
Abstract
Abstract The present invention provides a method of testing and packaging a semiconductor chip. The semiconductor chip includes an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method includes using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer has an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.
Inventors
- 👤 Hermen Liu
- 👤 Yimin Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:42
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/27; H10P74/273; H10W; H10W72/00; H10W72/20; H10W72/01; H10W72/019; H10W72/071; H10W72/072; H10W72/07251; H10W72/075; H10W72/07551; H10W72/07553; H10W72/251; H10W72/29; H10W72/50; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A method of testing and packaging a semiconductor chip, the semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC, the method comprising: using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC; and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip wherein the testing area of the bonding pad is covered under the passivation layer and the passivation layer comprises an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.
Claim 2
Independent Claim
127 words
A method of testing and packaging a semiconductor chip, the semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC, the method comprising: using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC; and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip wherein the testing area of the bonding pad is covered under the passivation layer and the passivation layer comprises an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein the bonding pad is a metallic layer formed of aluminum (Al), copper (Cu) or alloy of aluminum.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein the alloy is formed of aluminum and copper with more than 95% of aluminum by weight.
Claim 5
Dependent Claim
52 words
The method of claim 1 wherein the bonding pad comprises a glue layer formed of titanium (Ti) positioned on the surface of the semiconductor chip, an aluminum alloy layer positioned on the glue layer, and an anti-reflection layer formed of titanium nitride (TiN) positioned on the surface of the aluminum alloy layer.
Claim 6
Dependent Claim
33 words
The method of claim 1 wherein the passivation layer comprises an inorganic passivation layer positioned on the surface of the semiconductor chip and an organic passivation layer positioned on the inorganic passivation layer.
Claim 7
Dependent Claim
19 words
The method of claim 5 wherein the inorganic passivation layer is formed of phosphosilicate glass (PSG) or silicon nitride.
Claim 8
Dependent Claim
14 words
The method of claim 5 wherein the organic passivation layer is formed of polyimide.
Claim 9
Dependent Claim
17 words
The method of claim 1 wherein the opening is formed by performing photolithographic and dry etching processes.
Claim 10
Dependent Claim
42 words
The method of claim 8 wherein the dry etching process is performed by injecting a mixed gas at a low pressure over which the mixed gas comprises sulfur hexafluoride (SF 6 ), fluoroform (CHF 3 ), and carbon tetrafluoride (CF 4 ).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-25 | 2004-12-25 | 2005-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-25 | 2008-12-25 | 2009-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-25 | 2012-12-25 | 2013-06-26 | $7700.00 | Window Closed / Lapsed |